Semiconductor memory device

ABSTRACT

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor memory devices and,specifically, to a clock synchronized type semiconductor memory devicewhich operates in synchronization with externally applied clock signals.More specifically, the present invention relates to a structure of asemiconductor memory device containing a cache, in which a dynamicrandom access memory (DRAM) having a large storage capacity serving as amain memory, and a static random access memory (SRAM) having smallstorage capacity serving as a cache memory are integrated on the samesemiconductor chip.

2. Description of the Background Art

Historical Review on Memory Environment in a Conventional DataProcessing System

(i) Usage of standard DRAM as a main memory

Operation speed of recent 16-bit or 32-bit microprocessing unit (MPU)has been so much increased as to have operation clock frequency as highas 25 MHz or higher. In a data processing system, a standard DRAM(Dynamic Random Access Memory) is often used as a main memory havinglarge storage capacity, since cost per bit is low. Although access timein the standard DRAM has been reduced, the speed of operation of the MPUhas been increased much faster than that of the standard DRAM.Consequently, in a data processing system using the standard DRAM as amain memory, increase of wait state is inevitable. The gap in speed ofoperation between MPU and the standard DRAM is inevitable because thestandard DRAM has the following characteristics.

(1) A row address and a column address are time divisionally multiplexedand applied to the same address pin terminals. The row address is takenin the device at a falling edge of a row address strobe signal/RAS. Thecolumn address is taken in the device at a falling edge of a columnaddress strobe signal/CAS. The row address strobe signal/RAS definesstart of a memory cycle and activates row selecting circuitry. Thecolumn address strobe signal/CAS activates column selecting circuitry.Since a prescribed time period called "RAS-CAS delay time (tRCD)" isnecessary from the time the signal/RAS is set to an active state to thetime the signal/CAS is set to the active state, there is a limit inreducing the access time, namely, there is a limit derived from addressmultiplexing.

(2) When the row address strobe signal/RAS is once raised to set theDRAM to a standby state, the row address strobe signal/RAS cannot fallto "L" again until a time period called a RAS precharge time (tRP) haslapsed. The RAS precharge time is necessary for surely prechargingvarious signal lines in the DRAM to predetermined potentials. Due to theRAS precharge time TRP, the cycle time of DRAM cannot be reduced. Inaddition, when the cycle time of the DRAM is reduced, the number ofcharging/discharging of signal lines in the DRAM is increased, whichincreases current consumption.

(3) The higher speed of operation of the DRAM can be realized by circuittechnique such as improvement of layout, increase of degree ofintegration of circuits, development in process technique and byapplicational improvement such as improvement in the method of driving.However, the speed of operation of the MPU is increased at much fasterrate than DRAM. The speed of operation of semiconductor memories ishierarchical. For example, there are high speed bipolar RAMs usingbipolar transistors such as ECLRAMs (Emitter Coupled RAM) and StaticRAM, and relatively low speed DRAMs using MOS transistors (insulatedgate type field effect transistors). It is very difficult to expect theoperation speed (cycle time) as fast as several tens ns (nano seconds)in a standard DRAM formed of MOS transistors.

There have been various applicational improvements to stop the gapbetween speed of operations of the MPU and the standard DRAM. Suchimprovements mainly comprise the following two approaches.

(1) Use of high speed mode of the DRAM and interleave method

(2) External provision of a high speed cache memory (SRAM).

The first approach (1) includes a method of using a high speed mode suchas a static column mode or a page mode, and a method of combining thehigh speed mode and the interleave method. In the static column mode,one word line (one row) is selected, and thereafter only the columnaddress is changed successively, to successively access memory cells ofthis row. In the page mode, one word line is selected, and then columnaddresses are successively taken by toggling the signal/CAS tosuccessively access memory cells connected to the selected one wordline. In either of these modes, memory cells can be accessed withouttoggling the signal/RAS, enabling higher speed accessing than the normalaccess using the signals/RAS and/CAS.

In the interleave method, a plurality of memories are provided inparallel to a data bus, and by alternately or successively accessing theplurality of memories, the access time is reduced in effect. The use ofhigh speed mode of the DRAM and combination of the high speed mode andthe interleave method have been known as a method of using the standardDRAM as a high speed DRAM in a simple and relatively effective manner.

The second approach (2) has been widely used in a main frame art. A highspeed cache memory is expensive. However, in the field of personalcomputers in which high performance as well as low cost are desired,this approach is employed in some parts of the field with a sacrifice ofcost. There are three possible ways to provide the high speed cachememory. Namely,

(a) the high speed cache memory is contained in the MPU itself;

(b) the high speed cache memory is provided outside the MPU; and

(c) the high speed cache memory is not separately provided but the highspeed mode contained in the standard DRAM is used as a cache (the highspeed mode is used as a pseudo cache memory). When a cache hit occurs,the standard DRAM is accessed in the high speed mode, and at the time ofa cache miss, the standard DRAM is accessed in the normal mode.

The above mentioned three ways (a) to (c) have been employed in the dataprocessing systems in some way or other. In most MPU systems, thememories are organized in a bank structure and interleaving is carriedout on bank by bank basis in order to conceal the RAS precharge time(TRP) which is inevitable in the DRAM, in view of cost. By this method,the cycle time of the DRAM can be substantially one half that of thespecification value.

The method of interleave is effective only when memories aresequentially accessed. When the same memory bank is to be continuouslyaccessed, it is ineffective. Further, substantial improvement of theaccess time of the DRAM itself cannot be realized. The minimum unit ofthe memory must be at least 2 banks.

When the high speed mode such as the page mode or the static column modeis used, the access time can be reduced effectively only when the MPUsuccessively accesses a certain page (data of a designated one row).This method is effective to some extent when the number of banks iscomparatively large, for example 2 to 4, since different rows can beaccessed in different banks. When the data of the memory requested bythe MPU does not exist in the given page, it is called a "miss hit"(cache miss). Normally, a group of data are stored in adjacent addressesor sequential addresses. In the high speed mode, a row address, which isone half of the addresses, has been already designated, and thereforepossibility of "miss hit" is high.

When the number of banks becomes as large as 30 to 40, data of differentpages can be stored in different banks, and therefore the "miss hit"rate is remarkably reduced. However, it is not practical to provide 30to 40 banks in a data processing system. In addition, if a "miss hit"occurs, the signal/RAS is raised and the DRAM must be returned to theprecharge cycle in order to re-select the row address, which sacrificesthe characteristic of the bank structure.

In the above described second method (2), a high speed cache memory isprovided between the MPU and the standard DRAM. In this case, thestandard DRAM may have relatively low speed of operation. Standard DRAMshaving storage capacities as large as 4M bits or 16M bits have come tobe used. In a small system such as a personal computer, the main memorythereof can be formed by one or several chips of Standard DRAMs.External provision of the high speed cache memory is not so effective insuch a small system in which the main memory can be formed of onestandard DRAM. If the standard DRAM is used as the main memory, the datatransfer speed between the high speed cache memory and the main memoryis limited by the number of data input/output terminals of the standardDRAM, which constitutes a bottleneck in increasing the speed of thesystem.

When the high speed mode is used as a pseudo cache memory, the speed ofoperation thereof is slower than the high speed cache memory, and it isdifficult to realize the desired system performance.

(ii) Consideration on a conventional cache containing DRAM

Provision of the high speed cache memory (SRAM) in the DRAM is proposedas a method of forming.a relatively inexpensive and small system, whichcan solve the problem of sacrifice of system performance when theinterleave method or the high speed operation mode is used. Morespecifically, a single chip memory having a hierarchical structure of aDRAM serving as a main memory and a SRAM serving as a cache memory hasbeen conceived. The one-chip memory having such a hierarchical structureis called a cache DRAM (CDRAM). The CDRAM will be described withreference to FIGS. 1 through 4.

FIG. 1 shows a structure of a main portion of a conventional standard 1megabit DRAM. As shown in FIG. 1, the DRAM comprises a memory cell array500 including a plurality of memory cells MC arranged in a matrix ofrows and columns. A row of memory cells are connected to one word lineWL. A column of memory cells MC are connected to one column line CL.Normally, the column line CL is formed by a pair of bit lines. A memorycell MC is positioned at a crossing of one of the pair of bit lines andone word line WL. In a 1M DRAM, the memory cells MC are arranged in amatrix of 1024 rows×1024 columns. Namely, the memory cell array 500includes 1024 word lines WLs and 1024 column lines CLs (1024 pairs ofbit lines).

The DRAM further comprises a row decoder 502 which decodes an externallyapplied row address (not shown) for selecting a corresponding row Of thememory cell array 500; a sense amplifier which detects and amplifiesdata of the memory cell connected to the word line selected by the rowdecoder 502; and a column decoder which decodes an externally appliedcolumn address (not shown) for selecting a corresponding column of thememory cell array 502. In FIG. 1, the sense amplifier and the columndecoder are denoted by one block 504. If the DRAM has a ×1 bit structurein which input/output of data is effected bit by bit, one column line CL(a bit line pair) is selected by the column decoder.

If the DRAM has a ×4 bit structure in which input/output of data iseffected 4 bits by 4 bits, 4 column lines CL are selected by the columndecoder. One sense amplifier is provided for each column line (bit linepair) CL in the block 504.

In memory access for writing data to or reading data from the memorycell MC in the DRAM, the following operation is carried out. First, arow address is applied to the row decoder 502. The row decoder 502decodes the row address and raises the potential of one word line WL inthe memory cell array 500 to "H". Data of the 1024 bits of memory cellsMC connected to the selected word line WL are transmitted tocorresponding column lines CL. The data on the column lines CL areamplified by sense amplifiers included in the block 504. Selection of amemory cell to which the data is written or from which the data is readout of the memory cells connected to the selected word line WL iscarried out by a column selection signal from the column decoderincluded in the block 504. The column decoder decodes column addresssignals (more accurately, internal column address signals), andgenerates a column selecting signal for selecting the correspondingcolumn in the memory cell array 500.

In the above described high speed mode, column addresses aresuccessively applied to the column decoder included in the block 504. Inthe static column mode operation, column addresses applied atpredetermined time intervals are decoded as new cole addresses by thecolumn decoder, and the corresponding memory cell out of the memorycells connected to the selected word line WL is selected by the columnline CL. In the page mode, new column address is applied at everytoggling of the signal /CAS, and the column decoder decodes the columnaddress to select the corresponding column line. In this manner, one rowof memory cells MC connected to the selected word line WL can beaccessed at high speed by setting one word line WL at a selected stateand by changing the column addresses only.

FIG. 2 shows a general structure of a conventional 1M bit CDRAM.Referring to FIG. 2, the conventional CDRAM comprises, in addition tothe components of the standard DRAM shown in FIG. 1, SRAM 506 and atransfer gate 508 for transferring data between one row of the memorycell array 500 of the DRAM and the SRAM 506. The SRAM includes a cacheregister provided corresponding to each column line CL of the memorycell array 500 so as to enable simultaneous storage of data of one rowof the DRAM memory cell array 500. Therefore, 1024 cache registers areprovided. The cache register is formed by a static memory cell (SRAMcell).

In the structure of the CDRAM shown in FIG. 2, when a signalrepresenting a cache hit is externally applied, the SRAM 506 isaccessed, enabling access to the memory at high speed. At the time of acache miss (miss hit), the DRAM portion is accessed.

A CDRAM as described above having a DRAM of a large storage capacity anda high speed SRAM integrated on the same chip is disclosed in, forexample, Japanese Patent Laying-Open Nos. 60-7690 and 62-38590.

In the above described conventional CDRAM structure, column lines (bitline pairs) CL of the DRAM memory cell array 500 and column lines (bitline pairs) of the SRAM (cache memory) 506 are connected in one to onecorrespondence through a transfer gate 508. More specifically, in theabove described conventional CDRAM structure, data of the memory cellsconnected to one word line WL in the DRAM memory cell array 500 and thedata of the same number of SRAM cells as memory cells of one row of thememory cell array 500 are transferred bi-directionally andsimultaneously, through the transfer gate 508. In this structure, theSRAM 506 is used as a cache memory and the DRAM is used as a mainmemory.

The so called block size of the cache is considered to be the number ofbits (memory cells) the contents of which are rewritten in one datatransfer in SRAM 506. Therefore, the block size is the same as thenumber of memory cells which are physically coupled to one word line WLof DRAM memory cell array 500. As shown in FIGS. 1 and 2, when 1024memory cells are physically connected to one word line WL, the blocksize is 1024.

Generally, when the block size becomes larger, the hit rate isincreased. However, if the cache memory has the same size, the number ofsets is reduced in inverse proportion to the block size, and thereforethe hit rate is decreased. For example, when the cache size is 4K bitsand the block size 1024, the number of sets is 4. However, if the blocksize is 32, the number of sets is 128. Therefore, in the conventionalCDRAM structure, the block size is made too large, and the cache hitrate cannot be very much improved.

A structure enabling reduction in block size is disclosed in, forexample, Japanese Patent Laying-Open No. 1-146187. In this prior art,column lines (bit line pairs) of the DRAM array and the SRAM array arearranged in one to one correspondence, but they are divided into aplurality of blocks in the column direction. Selection of the block iscarried out by a block decoder. At the time of a cache miss (miss hit),one block is selected by the block decoder. Data are transferred onlybetween the selected DRAM block and the associated SRAM block. By thisstructure, the block size of the cache memory can be reduced to anappropriate size. However, there remains the following problem unsolved.

FIG. 3 shows a standard array structure of a 1M bit DRAM array. In FIG.3, the DRAM array is divided into 8 memory blocks DMB1 to DMB8. A rowdecoder 502 is commonly provided for the memory blocks DMB1 to DMB8 onone side in the longitudinal direction of the memory array. For each ofthe memory blocks DMB1 to DMB8, (sense amplifier+column decoder) blocks504-1 to 504-8 are provided.

Each of the memory blocks DMB1 to DMB8 has the capacity of 128K bits. InFIG. 3, one memory block DMB is shown to have 128 rows and 1024 column,as an example. One colunm line CL includes a pair of bit lines BL, /BL.

As shown in FIG. 3, when the DRAM memory cell array is divided into aplurality of blocks, one bit line BL (and/BL) becomes shorter. In datareading, charges stored in a capacitor (memory cell capacitor) in thememory cell are transmitted to a corresponding bit line BL (or/BL). Atthis time the amount of potential change generated on the bit line BL(or/BL) is proportional to the ratio Cs/Cb of the capacitance Cs of thememory cell capacitor to the capacitance Cb of the bit line BL (or/BL).If the bit line BL (or/BL) is made shorter, the bit line capacitance Cbcan be reduced. Therefore, the amount of potential change generated onthe bit line can be increased.

In operation, sensing operation in the memory block (memory block DMB2in FIG. 3) including the word line WL selected by the row decoder 502 iscarried out only, and other blocks are kept in a standby. state.Consequently, power consumption associated with charging/discharging ofthe bit lines during sensing operation can be reduced.

When the above described partial activation type CDRAM is applied to theDRAM shown in FIG. 3, a SRAM register and a block decoder must beprovided for each of the memory blocks DMB1 to DMB8, which significantlyincreases the chip area.

In this structure, only SRAM cache registers corresponding to theselected block operate, and therefore, efficiency in using the SRAMcache registers is low.

Further, the bit lines of the DRAM array and of the SRAM array are inone to one correspondence, as described above. When direct mappingmethod is employed as the method of mapping memories between the mainmemory and the cache memory, then the SRAM 506 is formed by 1024 cacheregisters arranged in one row, as shown in FIG. 2. In this case, thecapacity of the SRAM cache is 1K bits.

When 4 way set associative method is employed as the mapping method, theSRAM array 506 includes 4 rows of cache registers 506a to 506d as shownin FIG. 4. One of the 4 rows of cache registers 506a to 506d is selectedby the selector 510 in accordance with a way address. In this case, thecapacity of the SRAM cache is 4K bits.

As described above, the method of memory cell mapping between the DRAMarray and the cache memory is determined dependent on the internalstructure on the chip. When the mapping method is to be changed, thecache size also must be changed.

In both of the CDRAM structures described above, the bit lines of theDRAM array and the SRAM array are in one to one correspondence.Therefore, the column address of the DRAM array is inevitably the sameas the column address of the SRAM array. Therefore, full associativemethod in which memory cells of the DRAM array are mapped to anarbitrary position of the SRAM array is impossible in principle.

Another structure of a semiconductor memory device in which the DRAM andthe SRAM are integrated on the same chip is disclosed in Japanese PatentLaying-Open No. 2-87392. In this prior art, the DRAM array and the SRAMarray are connected through an internal common data bus. The internalcommon data bus is connected to an input/output buffer forinputting/outputting data to and from the outside of the device.Selected memory cells of the DRAM array and the SRAM array can bedesignated by separate addresses.

However, in this structure of the prior art, data transfer between theDRAM array and the SRAM array is carried out by an internal common databus, and therefore the number of bits which can be transferred at onetime is limited by the number of internal data bus lines, which preventshigh speed rewriting of the contents of the cache memory. Therefore, asin the above described structure in which the SRAM cache is providedoutside the standard DRAM, the speed of data transfer between the DRAMarray and the SRAM array becomes a bottleneck, preventing provision of ahigh speed cache memory system.

(iii) Consideration on a general clock synchronized type semiconductordevice for the problems of which the present invention includes thesolution.

A semiconductor memory device of an application specific IC (ASIC) orfor pipe line usage operates in synchronization with an external clocksignal such as a system clock. Operation mode of a semiconductor memorydevice is determined dependent on states of external control signals atrising or falling edge of the external clock signal. The external clocksignal is applied to the semiconductor memory device no matter whetherthe semiconductor memory device is being accessed or not. In thisstructure, in response to the external clock signal, input buffers orthe like receiving the external control signals, address signals anddata operate. In view of power consumption, it is preferred not to applythe external clock signal to the semiconductor memory device when thesemiconductor memory device is not accessed, or to elongate period ofthe external clock signal.

Generally, a row address signal and the column address signal areapplied multiplexed time divisionally to the DRAM. The row addresssignal and the column address signal are taken in the device insynchronization with the external clock signal. Therefore, when theconventional DRAM is operated in synchronization with the external clocksignal, it takes long time to take the row address signal and the columnaddress signal. Therefore, if low power consumption is given priority,the DRAM can not be operated at high speed.

If the conventional semiconductor memory device is operated insynchronization with the external clock signal, the speed of operationis determined solely by the external clock signal. If the semiconductormemory device is to be used where low power consumption is givenpriority over the high speed operation with the speed defined by theexternal clock signal, the conventional clock synchronized typeSemiconductor memory device can not be used for such application.

In a clock synchronized type semiconductor memory device, controlsignals and address signals are taken inside in synchronization with theclock signal. The control signals and address signals are taken insideby buffer circuits. Each buffer circuit is activated in synchronizationwith the clock signal and generates an internal signal corresponding tothe applied external signal. In a standby state or the like, validcontrol signals and valid address signals are not applied. However,external clock signals are continuously applied, causing unnecessaryoperations of the buffer circuits. This prevents reduction in powerconsumption during standby state. If the cycle period of the externalclock signal becomes shorter, the number of operations of the buffercircuits is increased, causing increase of power consumption duringstandby period. This is a serious problem in realizing low powerconsumption.

(iv) Consideration on the problems in refreshing operation in aconventional RAM

If the semiconductor memory device includes dynamic memory cells (DRAMcells), the DRAM cells must be periodically refreshed. The refresh modeof a DRAM generally includes an auto refresh mode and a self refreshmode, as shown in FIGS. 5 and 6.

FIG. 5 shows waveforms in the auto refresh operation. In the autorefresh mode, a chip select signal *CE is set to "H" and an externalrefresh designating signal *REF is set to "L". In response to a fall ofthe external refresh designating signal *REF, an internal control signalint. *RAS for driving row selecting circuitry falls to "L". In responseto the internal control signal int. *RAS, a word line is selected inaccordance with a refresh address generated from a built-in addresscounter, and memory cells connected to the selected word line arerefreshed. In the auto refresh mode, the timing of refreshing thesemiconductor memory device is determined by the externally appliedrefresh designating signal *REF. Therefore, whether or not refreshing isbeing carried out in the semiconductor memory device can be knownoutside the memory device.

FIG. 6 shows waveforms in the self refresh operation. In the selfrefresh mode, the chip select signal *CE is set to "H" and the externalrefresh designating signal *REF is set to "L". When the external refreshdesignating signal *REF falls to "L", the external control signal int.*RAS is generated, and a word line is selected in accordance with therefresh address from the built-in address counter. Thereafter, sensingoperation and rewriting of the memory cells connected to the selectedword line are carried out, and the memory cells connected to the wordline WL are refreshed.

The first cycle of self refreshing is the same as that of autorefreshing. When the chip select signal *CE is at "H" and the refreshdesignating signal *REF is kept at "L" for a predetermined time periodTF or longer, a refresh request signal is generated from a built-intimer. In response, the internal control signal int. *RAS is generated,the word line is selected and the memory cells connected to the selectedword line are refreshed. This operation is repeated while the refreshdesignating signal *REF is at "L". In the refreshing operation in theself refresh mode, the timings of refreshing are determined by a timercontained in the semiconductor memory device. Therefore, timings ofrefreshing can not be known from the outside. Normally, data can not beexternally accessed in the self refresh mode. Therefore, in the normalmode, self refreshing is not carried out. The self refresh mode isgenerally carried out at a standby for retaining the data.

Different semiconductor chips have different upper limits of refreshperiod necessary for retaining data (see NIKKEI ELECTRONICS, Apr. 6,1987, p. 170, for example). Generally, a guaranteed value for retainingdata is measured by testing the semiconductor memory device, and periodof a timer defining the self refresh cycle is programmed in accordancewith the guaranteed value, for carrying out self refreshing. When autorefresh mode and self refresh mode are selectively used, the guaranteedvalue for retaining data must be measured in order to determine the selfrefresh cycle. As shown in FIG. 6, in the self refresh mode, anoperation similar to that in the auto refreshing is carried out inresponse to the external refresh designating signal *REF, and thenrefreshing operation in accordance with the timer is carried out.Therefore, in an accurate sense, the self refresh cycle means a cyclecarried out after a lapse of a prescribed time period TF successive tothe auto refreshing. In the self refresh cycle, the refresh timing isdetermined by the contained timer, as described above, and the timingsof refreshing can not be known from the outside. Therefore, the selfrefresh cycle can not be used as a method of hidden refreshing, forexample, in a normal operation mode.

(v) Consideration on Array Arrangement in CDRAM and data transferbetween CDRAM and MPU (burst mode)

In a semiconductor memory device containing a DRAM array and a SRAMarray, it is preferred to transfer data at high speed from the DRAMarray to the SRAM array, so as to enable high speed operation. When dataare transferred from the DRAM array to the SRAM array, a row (word line)is selected, data of the memory cells connected to the selected wordline are detected and amplified, and then a column is selected in theDRAM array.

Generally, a row address signal and a column address signal are appliedmultiplexed to the DRAM. Therefore, increase of the speed of datatransfer from the DRAM array to the SRAM array is limited by thisaddress multiplexing. In this case, it is possible to apply the rowaddress and the cole address simply in accordance with a non-multiplexmethod to the DRAM. However, in that case, the number of terminals forinputting DRAM addresses are increased significantly. When the number ofterminals is increased, the chip size and the package size areincreased, which is not preferable.

In addition, data transfer from the DRAM array to the SRAM array must bedone after detection and amplification of the memory cell data by thesense amplifiers. Therefore, data transfer from the DRAM array to theSRAM array can not be carried out at high speed.

Further, some external operational processing units such as a CPU(Central Processing Unit) include a data transfer mode called a burstmode for carrying out data transfer at high speed. In the burst mode, agroup of data blocks are transferred successively. A block of data isstored at successively adjacent address positions. Since the burst modeis a high speed data transfer mode, the data blocks are stored in thecache memory in the semiconductor memory device containing a cache. Asemiconductor memory device containing a cache which can be easilyconnected to an operational processing unit having burst mode functionhas not yet been provided.

In order to implement a CDRAM, DRAM array and SRAM array are integratedon the same semiconductor chip. The semiconductor chip is housed in apackage. The layout of DRAM array and SRAM array as well as thegeometrical figures thereof on the chip are determined by thegeometrical figure and the physical dimensions of the housing package.

DRAM array and its associated circuitry occupy a major area of a chip inCDRAMbecause DRAM is employed as a large storage capacity memory. Thus,the size and figure of DRAM array are substantially determined by thesize and shape of the housing package.

In order to efficiently use the chip area, SRAM array should be arrangedor laid out on the chip efficiently. However, no consideration has madeon the configuration of SRAM array for implementing efficient chip areautilization and for housing CDRAM in a package of an arbitrary shape andsize.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a novel CDRAM withvarious operational functions and efficient chip layout.

Another object of the present invention is to provide a semiconductormemory device in which self refreshing can be carried out in the normalmode.

A further object of the present invention is to provide a semiconductormemory device allowing data transfer between DRAM array and a SRAM arrayat a high speed and with less power consumption.

A further another object of the present invention is to provide a clocksynchronized type semiconductor memory device in which power consumptionat standby mode can be significantly reduced.

A still further object of the present invention is to provide asemiconductor memory device which can be accessed at high speed even ata cache miss (miss hit).

A still further object of the present invention is to provide asemiconductor memory device containing a cache which can be easilyconnected to an arithmetic operation unit having burst mode function.

A still further object of the present invention is to provide asemiconductor memory device which operates at high speed even if theperiod of external clock signals is made longer.

A still further object of the present invention is to provide a clocksynchronized type semiconductor memory device which surely operates evenif the period of the external clock signal is made longer or even if theexternal clock signal is generated intermittently.

A still further object of the present invention is to provide asemiconductor memory device containing a cache which operates at highspeed without malfunction with low power consumption.

A still further object of the present,invention is to provide asemiconductor memory device containing a cache which operates insynchronization with clocks, and operates at high speed withoutmalfunction under low power consumption.

A still further object of the present invention is to provide asemiconductor memory device which can be readily applied to use wherehigh speed operation is given priority and to use where low powerconsumption is given priority.

A still further object of the present invention is to provide asemiconductor memory device containing a cache which easily realizeshigh speed operation and low power consumption dependent on the intendeduse.

A still further object of the present invention is to provide asemiconductor memory device containing a cache operating insynchronization with clocks which easily realizes both high speedoperation and low power consumption dependent on intended use.

A still further another object of the present invention is to provide anarray arrangement which allows effective use of chip area.

Yet another object of the present invention is to provide an SRAM arrayarrangement having a flexible array structure which can easilycorrespond to an arbitrary shape of the DRAM array.

A yet further object of the present invention is to provide asemiconductor memory device containing a cache having an arrayarrangement having high density and suitable for high degree ofintegration.

The present invention includes various aspects each of which is recitedindependently of others in the following.

A semiconductor memory device in accordance with a first aspect of thepresent invention includes a DRAM array having dynamic memory cells;means for generating a refresh address; an automatic refresh means forrefreshing the DRAM array in response to an external refreshdesignation; timer means measuring time for outputting a refresh requestevery prescribed timing; refresh means for refreshing the DRAM array inresponse to the refresh request from the timer means; refresh modesetting means for setting the refresh mode to either the auto refresh orself refresh mode; and input/output switching means for setting one pinterminal to a refresh designating input terminal or to a self refreshexecution designating output terminal, in accordance with the refreshmode set by refresh mode setting means. The timer means is activatedwhen self refresh mode is set by the refresh mode setting means.

In accordance with a second aspect of the present invention, thesemiconductor memory device comprises first and second memory cellarrays each including a plurality of memory cells arranged in rows andcolumns; a first row address input terminal for receiving a first rowaddress for designating a row of the first memory cell array; a firstcolumn address input terminal for receiving a first column address fordesignating a column of the first memory cell array; a second rowaddress input terminal for receiving a second row address fordesignating a row of the second memory cell array; and a second columnaddress input terminal for receiving a second column address fordesignating a column of the second memory cell array. The first rowaddress input terminal and the first column address input terminalinclude input terminals different from each other. The second rowaddress input terminal and the second column address input terminalinclude input terminals which are different from each other. The firstcolumn address input terminal includes a pin arrangement which is sharedwith at least one of the second row address input terminal and thesecond column address input terminal.

In accordance with the third aspect of the present invention, thesemiconductor memory device includes first and second memory cell arrayseach including a plurality of memory cells arranged in rows and columns;first address means for generating a first internal row address signaland a first internal column address signal for designating a row and acolumn of the first memory cell array in accordance with an externaladdress; and second address means for generating a second internal rowaddress and a second internal column address for designating a row and acolumn of the second memory cell array in accordance with the externaladdress. The first and second address means are activated insynchronization with an external clock signal, and simultaneouslygenerates the first internal row address signal, the first internalcolumn address signal, the second internal row address signal and thesecond internal column address signal in accordance with the timingdetermined by the clock signal.

The semiconductor memory device in accordance with the fourth aspect ofthe present invention includes a DRAM array including a plurality ofdynamic memory cells arranged in rows and columns; an SRAM arrayincluding a plurality of static memory cells arranged in rows andcolumns; data transfer means provided separate from an internal datatransmitting line for transferring data between the DRAM array and theSRAM array; sense amplifier means for detecting and amplifyinginformation of the selected memory cells of the DRAM array; and controlmeans responsive to a transfer designation from the DRAM array to theSRAM array for activating the transferring means at a timing earlierthan the timing of activating the sense amplifier means. Bit line dataof the DRAM array are transmitted directly to the transfer means, notthrough the internal data line.

The semiconductor memory device in accordance with the fifth aspect ofthe present invention includes a DRAM array including a plurality ofdynamic memory cells arranged in rows and columns; an SRAM arrayincluding a plurality of static memory cells arranged in rows andcolumns; amplifying means provided for each column of the DRAM array foramplifying signals on the corresponding column; sense amplifier meansfor amplifying and latching signals on the corresponding column; datatransfer means provided separate from an internal data transmitting linefor transferring data between the DRAM array and the SRAM array; meansresponsive to an address signal for selectively transmitting outputsfrom the amplifying means to the data transferring means; and controlmeans responsive to a data transfer designation for activating the datatransferring means before the activation of the sense amplifier means.The transfer mean includes means for forming a current mirror amplifyingmeans by supplying current to the amplifying means.

In accordance with a sixth aspect of the present invention, thesemiconductor memory device includes address input means for receivingaddress signals; address generating means responsive to a burst modedesignation for successively generating address signals at prescribedtimings; address selecting means receiving an output from address inputmeans and an output from address generating means, responsive to theburst mode designation for selectively passing the output of the addressgenerating means; and memory cell selecting means for selecting acorresponding memory cell out of a plurality of memory cells inaccordance with the output from the address selecting means.

In accordance with a seventh aspect of the present invention, thesemiconductor memory device includes address input means for receivingaddresses applied from an external arithmetic processing unit; addressgenerating means responsive to a burst mode designation.from theexternal arithmetic processing unit for generating addresses insynchronization with external clock signals; address selecting means forselectively passing an output from address input means or an output fromaddress generating means; and memory cell selecting means for selectinga corresponding memory Cell from the memory cell array in accordancewith the output from the address selecting means. The address selectingmeans selectively passes the output from the address generating means inresponse to the burst mode designation.

In accordance with the eighth aspect of the present invention, thememory device includes internal clock generating means responsive to anexternal clock signal for generating an internal clock signal, andsetting means for setting the internal clock generating means tooperation inhibited state in response to a standby state designatingsignal. The externally applied signal is taken in response to theinternal clock signal generated from the internal clock generatingmeans.

In accordance with a ninth aspect of the present invention, thesemiconductor device includes, in addition to those provided in theeighth aspect, refreshing means responsive to the inhibition of theinternal clock generation by the setting means for refreshing dynamicmemory cells.

A semiconductor memory device in accordance with a tenth aspect of thepresent invention includes a memory cell array having a plurality ofmemory cells arranged in rows and columns, and internal addressgenerating means receiving an external address signal for generating aninternal address signal. The external address signal includes anexternal row address signal for designating a row of the memory cellarray, and an external column address signal for designating a column ofthe memory cell array. The internal address generating means generatesinternal row address signal and internal column address signalcorresponding to the external row address signal and the external columnaddress signal, respectively.

The internal address generating means of the semiconductor memory devicein accordance with the tenth aspect of the present invention includesfirst address generating means which takes one of the above mentionedexternal row address signal and the external column address signal at afirst timing of an externally applied clock signal for generating afirst internal address signal corresponding to the taken externaladdress signal, and second address generating means which takes theother one of the external row address signal and the external columnaddress signal at a second timing of the externally applied clock signalfor generating a second internal address corresponding to the takenexternal address signal.

The first timing is determined by one of the rise and fall of theexternally applied clock signal, and the second timing is determined bythe other one of the rise and fall of the externally applied clocksignal.

The semiconductor memory device in accordance with an eleventh aspect ofthe present invention includes a memory cell array including a pluralityof memory cells, and address generating means receiving externallyapplied external address signal for generating an internal addresssignal corresponding to the received external address signal. Theexternal address signal designates a memory cell in the memory cellarray.

The semiconductor memory device in accordance with the eleventh aspectof the present invention further includes setting means responsive to anexternally applied timing designating signal for taking an address forsetting the timing for the address generating means to take theexternally applied address signal.

The address generating means takes the applied external address signalin accordance with the timing set by the setting means and generates theinternal address signal.

The semiconductor memory device in accordance with the twelfth aspect ofthe present invention includes a DRAM array including a plurality ofdynamic memory cells arranged in rows and columns, an SRAM arrayincluding a plurality of static memory cells arranged in a matrix ofrows and columns, and data transferring means provided between the DRAMarray and the SRAM array for transferring data between a selected memorycell of the DRAM array and a selected memory cell in the SRAM array.

Each row of the matrix of the SRAM array includes memory cells dividedinto n groups. The SRAM array further includes a plurality of word lineseach connected to memory cells of different group, n word lines beingarranged for each row in parallel to the row direction of the matrix.

A semiconductor memory device in accordance with a thirteenth aspect ofthe invention includes a high speed memory array having a plurality ofstatic type memory cells, a large storage capacity memory array having aplurality of memory cells, and data transfer means for transferring databetween a selected static type memory cell and a selected dynamic typememory cell.

The semiconductor memory device of the thirteenth aspect furtherincludes a data transfer bus for coupling the selected memory cell ofthe large storage capacity memory array with the data transfer means,clamping means for clamping the potential on the data transfer bus, andcontrol means responsive to an indication of data transfer from the highspeed memory array to the large storage capacity memory array forinhibiting a clamping operation of the clamping means.

A semiconductor memory device in accordance with a fourteenth aspect ofthe invention includes a high speed memory array having a plurality ofstatic type memory cells arranged in rows and columns, a large storagecapacity memory array having a plurality of dynamic type memory cells,and data transfer means for transfer data between a selected static typeand a selected dynamic type memory cell.

The semiconductor memory device in accordance with the fourteenth aspectfurther includes clamping means provided for each column of the highspeed memory array for clamping the potential of an associated colE, andcontrol means responsive to an indication of data transfer from thelarge storage capacity memory array to the high speed memory array forinhibiting a clamping operation by the clamping means.

According to the first aspect of the present invention, setting of theself refresh mode or the auto refresh mode is done by refresh modesetting means and one terminal is switched by the input/output switchingmeans to be a refresh designating input terminal in the auto refreshmode, and the self refresh execution designating output terminal in theself refresh mode. Therefore, even in the self refresh mode, refreshtiming can be known from the outside of the memory device, and selfrefresh mode can be utilized even in the normal mode.

In accordance with the second aspect of the present invention, since therow and column designating input terminals of the first and secondmemory cell array are provided separately for inputting the row addresssignals and the column address signals, the row address signals and thecolumn address signals to the first and second memory cell arrays can beapplied in the non-multiplexed manner. Part of the address signals tothe first memory cell array and address signals to the second memorycell array is applied to the same input terminal. Therefore, addressnon-multiplex method can be realized without increasing the number ofinput terminals.

According to the third aspect of the present invention, the first andsecond address means generate internal address signals by simultaneouslytaking address signals in synchronization with the external clocksignal, and therefore the clock synchronized type semiconductor memorydevice can be operated at high speed employing address non-multiplexmethod.

According to the fourth aspect of the present invention, data transfermeans is activated at an earlier timing than the activation of the senseamplifier in the DRAM array, and therefore data can be transferred fromthe DRAM array to the SRAM array at high speed.

According to the fifth aspect of the present invention, an output from acurrent mirror type amplifier is transmitted through the data transfermeans, and therefore the data transfer means can be activated withoutwaiting for the activation of the latch type sense amplifier, whichenables high speed data transfer from the DRAM array to the SRAM array.

According to the sixth aspect of the present invention, an internalcounter is activated in response to a burst mode designation from anexternal arithmetic processing unit, an output from the address counteris selected by a multiplexer to be utilized as an address signal, andthe multiplexer selects external address signals in a mode other thanthe burst mode. Therefore, a semiconductor memory device which can beeasily connected to an external arithmetic processing unit having burstmode function can be provided.

According to the seventh aspect of the present invention, a counter as abuilt-in address generator effects counting operation in synchronizationwith the external clock signal, the output from the counter is used asan address in the burst mode, and external address signals are taken andutilized in synchronization with an external clock signal in operationmodes other than the burst mode. Therefore, a clock synchronized typesemiconductor memory device which can be easily connected to an externaloperational processing unit having burst mode function can be realized.

According to the eighth aspect of the present invention, when generationof the internal clock signal is stopped at the standby state of theclock synchronized type semiconductor memory device, operations ofexternal signal input buffer and the like are stopped, so that powerconsumption in the standby state can be reduced.

According to the ninth aspect of the present invention, self refreshmode is activated when generation of the internal clock signal isstopped in the invention in accordance with the eighth aspect, andtherefore data of the DRAM array can be surely retained in the standbystate.

According to the tenth aspect of the present invention, since theexternal row address signals and the external column address signals aretaken at timings determined by the rise and fall of the external clocksignals, the external row address signal and the external column addresssignal can be taken by a single pulse of the external clock signal.Therefore, compared with a structure in which the external row addresssignal and the external column address signal are taken timedivisionally at timings determined by the rise of the external clocksignal, the external row address signal and the external column addresssignal can be taken sooner. Generally, operation of a clock synchronizedtype semiconductor memory device starts after the external addresssignals are taken. Therefore, the semiconductor memory device can beoperated at higher speed.

According to the eleventh aspect of the present invention, the timingfor taking the external address signals is determined by timinginformation set by setting means. Therefore, time required for takingthe external address signals can be set to an optimal value dependent onthe period of the external clock signals, and therefore higher speed ofoperation and lower power consumption can be flexibly realized.

In the SRAM array according to the twelfth aspect , memory cellsarranged in one row is divided into a plurality of groups. Memory cellsof each group is connected to a word line provided corresponding to eachgroup. Therefore, memory cells of one row of the SRAM array areconnected to a plurality of word lines. By adjusting the number n of thegroups of the memory cells of one row, an SRAM array having an arbitraryshape can be provided without changing the number of memory cellsconnected to one word line.

In the semiconductor memory device according to the thirteenth andfourteenth aspects, the control means is operable to inhibit theclamping operation of the clamping means provided at the data receivingside. Consequently, a current flow is prevented from flowing into thedata transfer means from the clamping means, resulting in reducedcurrent consumption.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

This application includes a large number of the drawing figures, and wefirst classify the figures according to the embodiments for the reader'sconvenience.

FIGS. 1 through 6 are related to a conventional memory device.

FIGS. 7 through 31 represent an array arrangement of CDRAM of thepresent invention.

FIGS. 32 represents an overall view of a functional construction of theCDRAM.

FIGS. 33 through 43B represent data outputting operation of the CDRAM.

FIGS. 44 through 60D represents data transfer between DRAM array andSRAM array.

FIGS. 61 through 70 represent modified data transfer arrangement withclamping circuitry.

FIGS. 71 through 75 represent peripheral circuitry of the CDRAM.

FIGS. 76 to 80 represent the usage of CDRAM in a system.

FIGS. 81 through 104 represent specific operation modes of the CDRAM.

FIG. 105 shows an overall construction of another CDRAM according to thepresent invention.

FIGS. 106 through 118 are related to high speed and low power operationmodes.

FIGS. 119 through 161 represent specific operations of another CDRAM.

FIGS. 162 through 175 represent selective usage of the auto-refreshingand self refreshing.

FIGS. 176 through 185 represent common usage of DRAM column address andSRAM row address.

FIGS. 186 through 193 represent separated I/O structure type DRAM arrayof another CDRAM.

FIGS. 194 through 196 represent modified separated IO array architectureCDRAM for fast data transfer by means of clamping circuitry.

FIGS. 197 through 201 represent burst mode operation in CDRAM's of thepresent invention.

FIGS. 202 through 214 represent sleep mode operation in CDRAMs of thepresent invention.

FIG. 215 summarizes the internal operations of another CDRAM.

Now, respective figures are described in the following.

FIG. 1 shows a structure of a memory array in a conventional dynamicsemiconductor memory device.

FIG. 2 shows a structure of an array portion in a conventionalsemiconductor memory device containing a cache.

FIG. 3 shows, as an example, a layout of the cache and the DRAM array inthe conventional semiconductor memory device containing a cache.

FIG. 4 shows a structure of a cache when 4 way set associative method isrealized by the conventional semiconductor memory device containing acache.

FIG. 5 is a diagram of signal waveforms showing the operation in theautomatic refreshing in the conventional semiconductor memory device.

FIG. 6 is a diagram of signal waveforms showing self refreshingoperation in the conventional semiconductor memory device.

FIG. 7 schematically shows a structure of a memory array portion of thesemiconductor memory device according to an embodiment of the invention.

FIG. 8 shows detailed structure of the memory array shown in FIG. 7.

FIG. 9 shows another example of the structure of the array arrangementin the semiconductor memory device according to an embodiment of theinvention.

FIG. 10 shows array arrangement of a semiconductor memory devicecontaining a 4M bit DRAM and a 16K bit SRAM.

FIG. 11 shows layout of DRAM array signal lines in one memory block ofthe semiconductor memory device shown in FIG. 10.

FIG. 12 schematically shows structures of a bit line and a word linerelated to a memory cell of the DRAM shown in FIG. 10.

FIG. 13 schematically shows a structure of a word line in thesemiconductor memory device of FIG. 10.

FIG. 14 shows layout of signal lines in the semiconductor memory deviceshown in FIG. 10.

FIG. 15 shows a structure of an SRAM array of the semiconductor memorydevice shown in FIG. 5.

FIG. 16 shows a structure of a conventional SRAM cell.

FIG. 17 is a diagram of signal waveforms showing the operation of theSRAM cell shown in FIG. 16.

FIG. 18 shows an example of a shape of a package for a semiconductormemory device containing a cache, and SRAM array and DRAM arrayarrangements contained therein.

FIG. 19 shows problems of the general SRAM array.

FIG. 20 is a diagram showing problems of the general SRAM arrayarrangement.

FIG. 21 shows a principle of the SRAM array arrangement of the presentinvention.

FIG. 22 shows, in comparison, the arrangement of the SRAM array of thepresent invention and the prior art arrangement.

FIG. 23 shows a pattern layout of the SRAM cell shown in FIG. 21.

FIG. 24 shows an SRAM array structure of the semiconductor memory devicecontaining a cache in accordance with one embodiment of the presentinvention.

FIG. 25 shows an example of a transfer gate circuit structure shown inFIG. 24.

FIG. 26 shows an example of a specific structure of the selectingcircuit shown in FIG. 25.

FIG. 27 shows a structure of the SRAM array arrangement and a structureof a transfer gate circuit employed for that SRAM arrangement.

FIG. 28 shows a specific structure of a transfer path from the SRAMarray to the DRAM array of the transfer gate circuit shown in FIG. 27.

FIG. 29 shows a detailed structure of the data transfer path from theDRAM array to the SRAM array of the transfer gate circuit shown in FIG.27.

FIG. 30 is a diagram of signal waveforms showing the operation of thetransfer gate circuit shown in FIGS. 27 to 29.

FIG. 31 shows a pin arrangement and a package for containing thesemiconductor memory device shown in FIG. 5.

FIG. 32 shows functionally the whole structure of a semiconductor memorydevice containing a cache in accordance with one embodiment of thepresent invention.

FIG. 33 shows manner of connections of the bit lines in the DRAM arrayand bit lines in the SRAM array with internal data line in thesemiconductor memory device shown in FIG. 32.

FIG. 34 shows an example of a structure of a data input/output circuitof the semiconductor memory device shown in FIG. 32.

FIG. 35 shows another example of the data input/output circuit of thesemiconductor memory device shown in FIG. 32.

FIG. 36 shows a further example of the data input/output circuit of thesemiconductor memory device shown in FIG. 32.

FIG. 37 shows a circuit structure for setting data output mode of thesemiconductor memory device shown in FIG. 32.

FIG. 38 shows a structure of an output circuit shown in FIG. 36.

FIG. 39 shows an example of a specific structure of a latch circuitshown in FIG. 37.

FIG. 40 is a block diagram showing a structure of an output controlcircuit shown in FIG. 36.

FIG. 41 shows timings of operations in latch output mode of the circuitshown in FIG. 37.

FIG. 42 shows timings of operations in register output mode of thecircuit shown in FIG. 37.

FIG. 43 shows timing of operations in transparent output mode of thecircuit shown in FIG. 37.

FIG. 44 shows an example of a specific structure of a data transfercircuit in the semiconductor memory device shown in FIG. 32.

FIG. 45 is a diagram of signal waveforms showing data transfer operationfrom the DRAM array to the SRAM array when the transfer gate circuitshown in FIG. 44 is employed.

FIG. 46 is a diagram of signal waveforms showing data transfer operationfrom the SRAM array to the DRAM array.

FIG. 47 is another diagram of signal waveforms showing data transferoperation from the DRAM array to the SRAM array when the bi-directionaldata transfer circuit shown in FIG. 44 is employed.

FIGS. 48A through 48F show, as an example, data transfer operation at acache miss in the semiconductor memory device shown in FIG. 32.

FIG. 49 shows another example of the structure of the bi-directionaltransfer gate circuit.

FIG. 50 shows specific structure of the circuit shown in FIG. 49.

FIG. 51 shows data transfer operation from the DRAM array to the SRAMarray by the circuit shown in FIGS. 49 and 50.

FIGS. 52A through 52D show, as an example, data transfer operation shownin FIG. 51.

FIG. 53 is a diagram of signal waveforms showing data transfer operationfrom the SRAM array to the DRAM array when the data transfer circuitshown in FIGS. 49 and 50 is employed.

FIG. 54 shows, as an example, data transfer operation shown in FIG. 53.

FIG. 55 is a diagram of signal waveforms showing data transfer operationfrom the DRAM array to the SRAM array at a cache miss reading, when thetransfer gate circuit shown in FIGS. 49 and 50 is employed.

FIGS. 56A through 56F show, as an example, data transfer operation shownin FIG. 55.

FIG. 57 shows another example of the structure of the bi-directionaldata transfer gate.

FIG. 58 shows detailed structure of the circuit shown in FIG. 57.

FIG. 59 is a diagram of signal waveforms showing data transfer operationfrom the DRAM array to the SRAM array when the circuit of FIG. 57 isemployed.

FIGS. 60A through 60D show, as an example, data transfer operation shownin FIG. 59.

FIG. 61 shows a modified array arrangement of CDRAM with clampingcircuitry.

FIG. 62 shows an equivalent arrangement to the arrangement of FIG. 61.

FIG. 63 shows a specific construction of the bidirectional transfer gateof FIG. 62.

FIG. 64 is a waveform diagram showing data transfer from DRAM to SRAMwith the transfer gate of FIG. 63.

FIG. 65 is a waveform diagram showing data transfer from SRAM to DRAMwith the transfer gate of FIG. 63.

FIG. 66 shows another construction of the bidirectional transfer gate ofFIG. 63.

FIG. 67 shows further another construction of the bidirectional transfergate of FIG. 62.

FIG. 68 is a waveform diagram showing data transfer from DRAM to SRAMwith the transfer gate of FIG. 67.

FIG. 69 is a waveform diagram showing data transfer from the latchcircuit to DRAM with the transfer gate of FIG. 67.

FIG. 70 shows another construction of the clamping circuit.

FIG. 71 shows an example of the manner of allottance of DRAM addressesand SRAM addresses in the semiconductor memory device shown in FIG. 32.

FIG. 72 shows another structure for allotting DRAM addresses and SRAMaddresses in the semiconductor memory device shown in FIG. 32.

FIG. 73 shows a manner of connection between internal data lines andSRAM bit line pairs when addresses are allotted in the manner shown inFIG. 72.

FIG. 74 functionally shows the structure of the transfer gate controlcircuit shown in FIG. 32.

FIG. 75 shows functional structure of a DRAM driving circuit shown inFIG. 32.

FIG. 76 is a table showing combinations of control signals for effectingvarious operations realized by the semiconductor memory device shown inFIG. 10.

FIG. 77 shows combinations of command registers of the semiconductormemory device shown in FIG. 32 and control signals for selecting thecommand registers.

FIG. 78 shows, as an example, a function realized by the commandregister shown in FIG. 77.

FIG. 79 shows one example of a manner of connection between thesemiconductor memory device shown in FIG. 10 and an external CPU.

FIG. 80 shows another example of the manner of connection between thesemiconductor memory device containing a cache shown in FIG. 10 and anexternal CPU.

FIG. 81 shows timings of cache hit writing operation in thesemiconductor memory device shown in FIG. 10.

FIG. 82 shows timings showing cache hit reading operation in transparentoutput mode of the semiconductor memory device shown in FIG. 10.

FIG. 83 shows timings showing cache hit reading operation in latchoutput mode in the semiconductor memory device shown in FIG. 10.

FIG. 84 shows timings of cache hit reading operation in a registeroutput mode in the semiconductor memory device shown in FIG. 10.

FIG. 85 shows timings for setting a copy back operation in thesemiconductor memory device shown in FIG. 5.

FIG. 86 shows timings for setting a block transfer operation in thesemiconductor memory device shown in FIG. 10.

FIG. 87 shows timings for setting an array writing operation in thesemiconductor memory device shown in FIG. 10.

FIG. 88 shows timings of control signals for setting an array readingoperation in the semiconductor memory device shown in FIG. 10.

FIG. 89 shows timings for setting an array active cycle in thesemiconductor memory device shown in FIG. 10.

FIG. 90 shows timings of control signals for setting an array activeoperation accompanying a transparent output mode in the semiconductormemory device shown in FIG. 10.

FIG. 91 shows timings of control signals for setting an array activecycle accompanied with a latched output mode in the semiconductor memorydevice shown in FIG. 10.

FIG. 92 shows timings of control signals for setting an array activeoperation accompanied with the registered output mode in thesemiconductor memory device shown in FIG. 10.

FIG. 93 shows timings of an array read cycle in the transparent outputmode in the semiconductor memory device shown in FIG. 10.

FIG. 94 shows timings of array read cycle accompanied with the latchedoutput mode in the semiconductor memory device shown in FIG. 10.

FIG. 95 shows timings of array read cycle operation in the registeroutput mode in the semiconductor memory device shown in FIG. 10.

FIG. 96 shows timings of control signals for setting the refreshingoperation in the semiconductor memory device shown in FIG. 10.

FIG. 97 shows timings of various control signals for simultaneouslycarrying out the cache hit writing operation and refreshing in thesemiconductor memory device shown in FIG. 10.

FIG. 98 shows timings of control signals for setting refreshingoperation with cache hit reading in the transparent output mode of thesemiconductor memory device shown in FIG. 10.

FIG. 99 shows timings of control signals for setting refreshingoperation with cache reading in the latch output mode of thesemiconductor memory device shown in FIG. 10.

FIG. 100 shows timings of control signals for setting refreshingaccompanied with cache hit reading operation in the registered outputmode of the semiconductor memory device shown in FIG. 10.

FIG. 101 shows timings of control signals for setting a command registersetting cycle of the semiconductor memory device according to FIG. 10.

FIG. 102 illustrates state transitions showing the operation at a cachemiss of the semiconductor memory device shown in FIG. 10.

FIG. 103 illustrates state transitions showing the array accessoperation in the semiconductor memory device shown in FIG. 10.

FIG. 104 shows state transitions during refreshing operation of thesemiconductor memory device shown in FIG. 10.

FIG. 105 functionally shows a structure of a semiconductor memory devicein accordance with a second embodiment of the present invention.

FIG. 106 is a diagram of waveforms showing timings for taking DRAMaddresses of the semiconductor memory device shown in FIG. 105.

FIG. 107 shows effects provided by an address generating circuitincluded in the semiconductor memory device shown in FIG. 105.

FIG. 108 shows another effect of the address generating circuit shown inFIG. 105.

FIG. 109 shows a specific structure of the address generating circuitshown in FIG. 105.

FIG. 110 shows a specific structure of a row address strobe signalgenerating circuit shown in FIG. 109.

FIG. 111 shows a specific structure of a column address strobe signalgenerating circuit shown in FIG. 109.

FIG. 112 shows a specific structure of a row address latch shown in FIG.109.

FIG. 113 shows a specific structure of a column address latch shown inFIG. 109.

FIG. 114 shows a structure for setting timings for taking addresses ofthe circuit shown in FIG. 109.

FIG. 115 illustrates high speed operation of the address generatingcircuit shown in FIG. 109.

FIG. 116 illustrates an operation at a low power consumption mode of theaddress generating circuit shown in FIG. 109.

FIG. 117 shows another structure of the column address strobe signalgenerating circuit shown in FIG. 109.

FIG. 118 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 117.

FIG. 119 is a table showing operations realized by the semiconductormemory device shown in FIG. 105 and combinations of control signalstates for realizing these operations.

FIG. 120 shows manner of data transfer between the SRAM array and theDRAM array of the semiconductor memory device shown in FIG. 105.

FIG. 121 is a diagram of signal waveforms showing an operation at acache miss of the semiconductor memory device shown in FIG. 105.

FIG. 122 shows timings at a cache hit reading operation of thesemiconductor memory device shown FIG. 105.

FIG. 123 is a diagram of waveforms showing a cache hit writing operationat a low power consumption mode of the semiconductor memory device shownin FIG. 105.

FIG. 124 is a diagram of signal waveforms showing a cache hit readingoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 125 is a diagram of signal waveforms showing a cache miss writingoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 126 is a diagram of signal waveforms showing a array writingoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 127 is a diagram of signal waveforms showing an array writingoperation accompanied with cache hit reading at a low power consumptionmode of the semiconductor memory device shown in FIG. 105.

FIG. 128 is a diagram of signal waveforms showing an array writingoperation accompanied with cache hit writing at a low power consumptionmode of the semiconductor memory device shown in FIG. 105.

FIG. 129 is a diagram of signal waveforms showing a direct array readingoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 130 is a diagram of signal waveforms showing a direct array writingoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 131 is a diagram of signal waveforms showing a refresh arrayoperation at a low power consumption mode of the semiconductor memorydevice shown in FIG. 105.

FIG. 132 is a diagram of signal waveforms showing a refresh arrayoperation accompanied with cache hit reading at a low power consumptionmode of the semiconductor memory device shown in FIG. 105.

FIG. 134 is a diagram of signal waveforms showing a refresh arrayoperation accompanied with cache hit writing at a low power consumptionmode of the semiconductor memory device shown in FIG. 105.

FIG. 134 is a diagram of signal waveforms showing a counter checkreading operation at a low power consumption mode of the semiconductormemory device shown in FIG. 105.

FIG. 135 is a diagram of signal waveforms showing a counter checkwriting operation at the low power consumption mode of thesemiconductor.memory device shown in FIG. 105.

FIG. 136 is a diagram of signal waveforms showing a command registersetting operation at the low power consumption mode of the semiconductormemory device shown in FIG. 105.

FIG. 137 shows an example of a specific operation sequence at the lowpower consumption mode of the semiconductor memory device shown in FIG.105.

FIG. 138 shows another example of the specific operation sequence at thelow power consumption mode of the semiconductor memory device shown inFIG. 105.

FIG. 139 is a diagram of signal waveforms showing a cache hit readingoperation in the transparent output mode in high speed operation moderealized by the semiconductor memory device shown in FIG. 105.

FIG. 140 is a diagram of signal waveforms showing the cache hit readingoperation in the latched output mode of the high speed operation moderealized by the semiconductor memory device shown in FIG. 105.

FIG. 141 is a diagram of signal waveforms showing a cache hit readingoperation in the registered output mode in the high speed operation moderealized by the semiconductor memory device shown in FIG. 105.

FIG. 142 is a diagram of signal waveforms showing the cache hit writingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 143 is a diagram of signal waveforms showing the cache miss readingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 144 is a diagram of signal waveforms showing the cache miss readingoperation accompanied with the latched output mode in the high speedoperation mode realized by the semiconductor memory device shown in FIG.105.

FIG. 145 is a diagram of signal waveforms showing the cache miss readingoperation in the registered output mode in the high speed operation moderealized by the semiconductor memory device shown in FIG. 105.

FIG. 146 is a diagram of signal waveforms showing the cache miss writingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 147 is a diagram of signal waveforms showing the array writingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 148 is a diagram of signal waveforms showing the array writingoperation accompanied with the cache hit reading in the high speedoperation mode realized by the semiconductor memory device shown in FIG.105.

FIG. 149 is a diagram of signal waveforms showing the array writingoperation accompanied with the cache hit reading in the latched outputmode in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 150 is a diagram of signal waveforms showing the array writingoperation accompanied with the cache hit reading in accordance with theregistered output mode in the high speed operation mode realized by thesemiconductor memory device shown in FIG. 105.

FIG. 151 is a diagram of signal waveforms showing the array writingoperation accompanied with the cache hit writing in the high speedoperation mode in the semiconductor memory device shown in FIG. 105.

FIG. 152 is a diagram of signal waveforms showing a direct array readingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 153 is a diagram of signal waveforms showing a direct array writingoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 154 is a diagram of signal waveforms showing the refresh arrayoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 155 is a diagram of signal waveforms showing the refreshingoperation accompanied with cache hit reading in the high speed operationmode realized by the semiconductor memory device shown in FIG. 105.

FIG. 156 is a diagram of signal waveforms showing the refresh arrayoperation accompanied with cache hit writing in the high speed operationmode realized by the semiconductor memory device shown in FIG. 105.

FIG. 157 is a diagram of signal waveforms showing the counter checkoperation in the high speed operation mode realized by the semiconductormemory device shown in FIG. 105.

FIG. 158 is a diagram of signal waveforms showing the counter checkwriting operation in the high speed operation mode realized by thesemiconductor memory device shown in FIG. 105.

FIG. 159 is a diagram of signal waveforms showing the command registersetting operation in the high speed operation mode realized by thesemiconductor memory device shown in FIG. 105.

FIG. 160 is a diagram of signal waveforms showing an example of anoperation sequence carried out in the high speed operation mode by thesemiconductor memory device shown in FIG. 105.

FIG. 161 shows another example of the operation sequence realized in thehigh speed operation mode by the semiconductor memory device shown inFIG. 105.

FIG. 162 shows a structure which can selectively effect self refreshingand auto-refreshing in the semiconductor memory device shown in FIG. 32or FIG. 105.

FIG. 163 is a block diagram showing a specific structure of the clockgenerator shown in FIG. 162.

FIG. 164 shows an example of a specific structure of the input/outputswitching circuit and a command register shown in FIG. 162.

FIG. 165 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 162.

FIG. 166 shows another example of the structure of the circuit shown inFIG. 162.

FIG. 167 illustrates battery backup mode.

FIG. 168 is a block diagram showing a specific structure of a BBUcontrol shown in FIG. 166.

FIG. 169 shows a structure of the clock generator shown in FIG. 166 whenthe battery backup mode is employed.

FIG. 170 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 169.

FIG. 171 shows an example of a specific structure of a RASS generatingcircuit shown in FIG. 169.

FIG. 172 shows a structure when the structure of FIG. 162 is applied toa general DRAM.

FIG. 173 shows an example of a specific structure of the clock generatorshown in FIG. 172.

FIG. 174 shows another example of the structures of the input/outputswitching circuit and the command register shown in FIG. 162.

FIG. 175 shows another example of the structures of the input/outputswitching circuit and the command register shown in FIG. 162.

FIG. 176 shows another example of the manner of allotting addresses inthe semiconductor memory device shown in FIG. 32 or FIG. 105.

FIG. 177 shows connection between the address buffer circuit and theaddress decoder in accordance with the array allotting method shown inFIG. 176.

FIG. 178 shows an example of a specific structure of a determiningcircuit shown in FIG. 177.

FIG. 179 shows, as an example, positions of dividing address signallines in accordance with the address allotting method shown in FIG. 176.

FIG. 180 shows another example of the structure for realizing theaddress allotting method shown in FIG. 176.

FIG. 181 is a diagram of signal waveforms showing the operation of thesemiconductor memory device in accordance with the address allottingmethod shown in FIG. 176.

FIG. 182 shows timings of operations of the semiconductor memory devicein accordance with the address allottance shown in FIG. 176.

FIG. 183 shows, as an example, an operation of the semiconductor memorydevice in accordance with the address allotting method shown in FIG.176.

FIG. 184 shows, as an example, the manner of connection between anexternal CPU and the semiconductor memory device shown in FIG. 176.

FIG. 185 shows, as an example, the manner of connection between anexternal CPU and the semiconductor memory device in accordance with theaddress allotting method shown in FIG. 176.

FIG. 186 shows another example of the structure of the DRAM array.

FIG. 187 is a diagram of signal waveforms showing data transferoperation from the DRAM array to the SRAM array in the memory array andtransfer gate structure shown in FIG. 186.

FIG. 188 is a diagram of signal waveforms showing data transferoperation from the SRAM array to the DRAM array in the structure shownin FIG. 186.

FIG. 189 shows data transferring portion from the DRAM array to the SRAMarray of the transfer gate shown in FIG. 186.

FIG. 190 shows a circuit structure for transferring data from the SRAMarray to the DRAM array of the transfer gate shown in FIG. 186.

FIG. 191 shows a circuit structure for generating a signal for driving acolumn selecting line in FIG. 186.

FIG. 192 shows a circuit structure for generating a block selectingsignal shown in FIG. 186.

FIG. 193 shows, as an example, an array allotting method for effectivelydriving the array structure shown in FIG. 186.

FIG. 194 shows a modified separated IO DRAM array arrangement ofCDRAMwith clamping circuitry.

FIG. 195 is a waveform diagram showing data transfer from DRAM to SRAMin CDRAM of FIG. 194.

FIG. 196 is a waveform diagram showing data transfer from SRAM (or thelatch) to DRAM in CDRAM of FIG. 194.

FIG. 197 shows a circuit structure for realizing data transfer in theburst mode.

FIG. 198 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 197.

FIG. 199 shows an example of a specific structure of the address countershown in FIG. 197.

FIG. 200 shows an example of a specific structure of a burst data numberstoring circuit shown in FIG. 197.

FIG. 201 shows a structure for driving a common semiconductor memorydevice in the burst mode.

FIG. 202 shows a specific structure of the address buffer of thesemiconductor memory device shown in FIG. 32 or FIG. 105.

FIG. 203 shows an example of a specific structure of the control clockbuffer shown in FIG. 32 or FIG. 105.

FIG. 204 is a diagram of signal waveforms showing an operation in asleep mode.

FIG. 205 is a block diagram showing a circuit structure for realizingthe sleep mode.

FIG. 206 shows an example of a specific structure of the internal clockgenerating circuit shown in FIG. 205.

FIG. 207 shows an example of a specific structure of the sleep controlcircuit shown in FIG. 205.

FIG. 208 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 207.

FIG. 209 shows a circuit structure for realizing self refreshing in thesleep mode.

FIG. 210 shows a structure of portions related to a refresh requestingsignal of the clock generator shown in FIG. 209.

FIG. 211 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 209.

FIG. 212 shows another example of a structure of the sleep controlcircuit shown in FIG. 205.

FIG. 213 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 212.

FIG. 214 shows, as an example, required conditions of the controlsignals E# and CI# for surely setting the sleep mode.

FIG. 215 is a table showing operations realized by the semiconductormemory device shown in FIG. 105 in combination with the states ofcontrol signals.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Array arrangement of DRAM and SRAM arrays in CDRAM are described withreference to FIGS. 7 through 23. In the arrangement, DRAM array includesa plurality of blocks to implement partial activation type operation.DRAM array includes local IO lines provided for respective blocks, andglobal IO lines each provided for blocks arranged in a row direction.SRAM array includes a plurality of SRAM cells arranged in a matrix. Datatransfer of a plurality of bits between DRAM array and SRAM array ismade through bidirectional transfer gate circuit and global IO lines.DRAM address and SRAM address can be set independently of each other.This arrangement allows first data transfer in any mapping schemebetween DRAM array and SRAM array, as the blocks arranged in a columndirection are simultaneously activated to communicate data withcorresponding global IO lines through local IO lines. Now, detailedexplanation will be made on specific DRAM and SRAM array arrangements.

[Array Arrangement 1]

FIG. 7 schematically shows a structure of a memory array portion of thesemiconductor memory device in accordance with one embodiment of thepresent invention. Referring to FIG. 7, the semiconductor memory devicecomprises a DRAM array 1 including dynamic memory cells arranged in amatrix of rows and columns, a SRAM array 2 including static memory cellsarranged in a matrix of rows and columns, and a bi-directional transfergate circuit 3 for transferring data between DRAM array 1 and SRAM array2.

DRAM array 1 includes, assuming that it has storage capacity of 1M bit,1024 word lines WL and 1024 pairs of bit lines BL and/BL. In FIG. 7, theDRAM bit line pair is denoted by DBL. DRAM array 1 is divided into aplurality of blocks along the row and column directions. In FIG. 7, DRAMarray 1 is divided into 8 blocks MBi1 to MBi8 (i=1 to 4) along thecolumn direction and divided into 4 blocks MB1j to MB4j (j=1 to 8) alongthe row direction, namely, it is divided into a total of 32 memoryblocks as an example.

8 blocks Mbi1 to Mbi8 divided in the column direction constitute a rowblock 11. 4 blocks MB1j MB4j divided in the row direction constitute acoluntn block 12. The memory blocks Mbi1 to Mbi8 included in one rowblock 11 share the same word line WL. The memory blocks MB1j to MB4jincluded in the same column block 12 shares a column selecting line CSL.A sense amplifier +I0 block 13 is provided for each of the memory blocksMB11 to MB18. The structure of sense amplifier +I0 block 13 will bedescribed later. Column selecting line CSL simultaneously selects twocolumns (two pairs of bit lines).

The semiconductor memory device further comprises a row decoder 14responsive to an address for selecting a corresponding one row from DRAMarray 1, and a column decoder 15 responsive to an applied column addressfor selecting one column selecting line CSL. Column blocks 12 areconnected to the bi-directional transfer gate circuit 13 through twopairs of I/O lines 16a and 16b which are independent and separate fromeach other.

SRAM array 2 includes 16 pairs of bit lines SBL which are connected to16 pairs of I/O lines through the bi-directional transfer gates circuit3, respectively. If SRAM array 2 has the capacity of 4K bit, it includes16 pairs of bit lines and 256 word lines. Namely, in SRAM array 2, onerow is comprised of 16 bits. SRAM array 2 is associated with a SRAM rowdecoder 21 for decoding a row address applied to the SRAM for selectingone row of SRAM array 2, a SRAM column decoder 22 for decoding anapplied column address and for selecting a corresponding column in SRAMarray 2, and a sense amplifier circuit 23 for amplifying and outputtingdata of the memory cell selected by SRAM row decoder 21 and SRAM columndecoder 22 in data reading.

The SRAM bit line pair SBL selected by SRAM column decoder 22 isconnected to a common data bus, and input/output of data with theoutside of the device is effected through an input/output buffer (notshown). Addresses applied to DRAM row decoder 14 and DRAM column decoder15 are independent of addresses applied to SRAM row decoder 21 and SRAMcolumn decoder 22, and are applied to mutually different address pinterminals from those for SRAM addresses. Data transfer operation of thesemiconductor memory device shown in FIG. 7 will be briefly described.

The operation of the DRAM portion will be described. First, inaccordance with an externally applied row address, row decoder 14carries out a row selecting operation and raises potential of one wordline DWL to "H". Data are read to corresponding 1024 bit lines BL(or/BL) from memory cells connected to the selected one word line DWL.

Then, sense amplifiers (included in the block 13) of row block 11including the selected word line DWL are activated at one time, anddifferentially amplify potential difference between each bit line pair.Only one of the four row blocks 11 is activated to reduce powerconsumption associated with charging/discharging of the bit lines duringthe sensing operation. (This operation, in which only the row blockincluding the selected row is activated, is called partial activationmethod.)

In accordance with an externally applied column address, DRAM columndecoder 15 carries out a column selecting operation and one columnselecting line CSL is set to the selected state in each column block 12.The column selecting line CSL selects two pairs of bit lines, and thetwo pairs of bit lines are connected to two pairs of I/O lines 16a and16b provided corresponding to the block. Consequently, a plurality ofbits (16 bits in this embodiment) of data are read to the plurality ofI/O line pairs 16a and 16b from DRAM array 1.

Operation of the SRAM portion will be described. In accordance with anexternally applied row address, SRAM row decoder 21 carries out rowselecting operation and selects one word line from SRAM array 2. Asdescribed above, 16 bits of memory cells are connected to one SRAM wordline. Therefore, by the selection of one word line, 16 static memorycells (SRAM cells) are connected to 16 pairs of bit lines SBL.

After 16 bit data have been transmitted to I/O line pairs 16a and 16bfor DRAM array 1, bi-directional transfer gate circuit 3 is turned ON,and 16 pairs of I/O lines 16a and 16b are connected to 16 pairs of bitlines SBL of the SRAM. Consequently, data which have been transmitted to16 pairs of I/O lines 16a and 16b are written to the 16 bits of memorycells which have been selected in SRAM array 2.

A sense amplifier circuit 23 and column decoder 22 provided in the SRAMare used to transfer data between the memory cells in SRAM array 2 andan input/output buffer for inputting/outputting external data.

It is possible to set addresses for selecting SRAM cells in SRAM array 2completely independent from addresses for selecting dynamic memory cells(DRAM cells) in DRAM array 1. Therefore, it is possible for the 16 bitsof memory cells selected in DRAM array 1 to exchange data with memorycells at an arbitrary position (row) of SRAM array 2. Therefore, all ofthe direct mapping method, set associative method and full associativemethod can be realized without changing the structure, or the arrayarrangement.

The principle of simultaneous transfer of 16 bits of data from the DRAMto the SRAM has been described. Simultaneous transfer of 16 bits of datafrom SRAM array 2 to DRAM array 1 is carried out in the same manner,except that the direction of data flow through the bi-directionaltransfer gate circuit 3 is reversed. The structure and operation of thesemiconductor memory device containing a cache in accordance with thepresent invention will be described in detail.

FIG. 8 shows a specific structure of a main portion of the semiconductormemory device shown in FIG. 7. FIG. 8 shows, as a representative, aportion related to data transfer of one memory block MBij of DRAM array.Referring to FIG. 8, DRAM memory block MBij includes a plurality of DRAMcells DMCs arranged in rows and columns. DRAM cell DMC includes onetransistor Q0 and one capacitor C0. A constant potential Vgg is appliedto one electrode (cell plate) of memory capacitor C0.

The memory block MBij further includes DRAM word lines DWL to each ofwhich one row of DRAM cells DMCs are connected, and DRAM bit line pairsDBL to each of which a column of DRAM cells DMCs are connected. The DRAMbit line pair DBL includes two bit lines BL and/BL. Signalscomplementary to each other are transmitted to bit lines BL and/BL. ADRAM cell DMC is arranged at a crossing of a DRAM word line DWL and aDRAM bit line pair DBL.

A DRAM sense amplifier DSA for detecting and amplifying potentialdifference on a corresponding bit line pair is provided for each of theDRAM bit line pairs DBL. Operation of DRAM sense amplifier DSA iscontrolled by a sense amplifier activating circuit SAK which generatessense amplifier driving signals φSAN and/φSAP in response to senseamplifier activating signals φSANE and/φSAPE. DRAM sense amplifier DSAincludes a first sense amplifier portion having p channel MOStransistors cross coupled for raising a bit line potential.which ishigher in a bit line pair to operational supply potential Vcc level inresponse to the signal /φSAP, and a second sense amplifier portionhaving n channel MOS transistors cross coupled for discharging potentialof a bit line in the pair which is at lower potential to, for example,the potential Vss of the ground potential level, in response to thesignal φSAN.

The sense amplifier activating circuit SAK includes a sense amplifieractivating transistor TR1 which is turned on in response to senseamplifier activating signal/φSAPE for activating the first senseamplifier portion of DRAM sense amplifier DSA, and a sense amplifieractivating transistor TR2 which is turned on in response to senseamplifier activating signal φSANE for activating the second senseamplifier portion of DRAM sense amplifier DSA. Transistor TR1 is formedby a P channel MOS transistor, while the transistor TR2 is formed by ann channel MOS transistor. When turned on, transistor TR1 transmits adriving signal/φSAP of the operational supply potential Vcc level to onesupply node of each sense amplifier DSA. When turned on, transistor TR2transmits a signal φSAN of the potential Vss level to the other supplynode of DRAM sense amplifier DSA.

Between a signal line/φSAP and the signal line φSAN to which signals/φSAP and φSAN are output from sense amplifier activating circuit SAK,an equalize transistor TEQ is provided for equalizing both signal linesin response to an equalize designating signal φEQ. Therefore, in thestandby state, sense amplifier driving signal lines /φSAP and φSAN areprecharged to an intermediate potential of (Vcc+Vss)/2. Signal lines andsignals transmitted thereto are represented by the same referencecharacters.

For each of the DRAM bit line pairs DBL, a precharge/equalize circuit PEwhich is activated in response to a precharge equalize signal φEQ forprecharging and equalizing bit lines of the corresponding bit line pairto a predetermined precharge potential Vb1 is provided.

DRAM memory block MBij further comprises a column selecting gate CSGprovided for each of the DRAM bit line pairs DBL and turned on inresponse to a signal potential on column selecting line CSL forconnecting the corresponding DRAM bit line pair DBL to a local I/O linepair LIO. A column selecting line CSL is commonly provided for two pairsof DRAM bit lines, and therefore, two DRAM bit line pairs DBL areselected simultaneously. In order to receive data from thesimultaneously selected two pairs of DRAM bit lines, two pairs of localI/O lines, that is, LIOa and LIOb are provided.

Memory block MBij further comprises IO gates IOGa and IOGb responsive toa block activating signal φBA for connecting the local I/O line pairsLIOa and LIOb to global I/O line pairs GIOa and GIOb, respectively.Column selecting line CSL extends in the row direction over one columnblock shown in FIG. 7, and global I/O line pair GIOa and GIOb alsoextend in the row direction over one column block. Local I/O line pairLIOa and LIOb extend only in the column direction in one memory block.

I/O lines 16a and 16b in FIG. 7 correspond to local I/O line pair LIOaand LIOb, IO gates IOGa and IOGb, and global I/O line pairs GIOa andGIOb, respectively.

SRAM comprises SRAM word lines SWL to each of which one row of SRAMcells SMCs are connected, SRAM bit line pairs SBL to each of which acolumn of SRAM cells SMCs are connected, and SRAM sense amplifiers SSAprovided corresponding to the SRAM bit line pairs SBL for detecting andamplifying potential difference between the corresponding bit line pair.

Bi-directional transfer gate circuit 3 comprises bi-directional transfergates BTGa and BTGb provided between SRAM bit line pair SBL and globalI/O line pair GIO. Both of bi-directional transfer gates BTGa and BTGbtransfer data between SRAM bit line pair SBL and global I/O line pairsGIOa and GIOb in response to data transfer designating signals φTSD andφTDS. Data transfer designating signal φTSD designates data transferfrom SRAM portion to DRAM portion, while data transfer designatingsignal φTDS designates data transfer from DRAM portion to SRAM portion.

[Array Arrangement 2]

FIG. 9 shows another example of the structure of the array arrangement.In the array arrangement of FIG. 9, an SRAM column decoder 22 isprovided between DRAM array 1 and SRAM array 2. An input/output buffer274 is connected to a column selected by SRAM column decoder 22 throughan internal data line 251. In the structure shown in FIG. 9, the columnselected by DRAM array 1 is connected to internal data line 251 throughthe bi-directional transfer gate. The connection between DRAM array 1and internal data line 251 through bi-directional transfer gate circuit3 may be effected by the column selecting gate provided in thebi-directional transfer gate by a column selecting signal from columndecoder 15 of the DRAM. The connection between DRAM array 1 and internaldata line 251 and connection between SRAM array 2 and internal data line251 will be described in detail later.

An address buffer 252 takes an address signal Aa applied externally inresponse to a chip enable signal E and generates an internal row.columnaddress signal int-Aa for designating a row.column of DRAM array 1.Address buffer 252 takes an externally applied address signal Ac inresponse to chip enable signal E and generates an internal row.columnaddress signal int-Ac for designating a row and a colunm of SRAM array2. External address signal Aa for DRAM array and address signal Ac forSRAM array are applied to address buffer 252 through separate terminals.

In this structure shown in FIG. 9, internal address int-Ac applied tothe row decoder 21 and column decoder 22 of SRAM and internal addressint-Aa applied to row decoder 14 and column decoder 15 of DRAM areapplied through independent paths. Therefore, by this structure,addresses of memory cells in SRAM array 2 and DRAM array 1 can beindependently designated.

In the structure shown in FIG. 9, a SRAM column decoder 22 is providedbetween bi-directional transfer gate circuit 3 and SRAM array 2. SRAMcolumn decoder 22 may be provided between bi-directional transfer gatecircuit 3 and DRAM array 1. Alternatively, a corresponding I/O line pairof DRAM array may be selected from I/O line pairs 16a, 16b of DRAM array1 by an output from DRAM column decoder 15 to connect the same tointernal common data bus 251, and SRAM bit line pair SBL may beconnected to internal data transmitting line 251 by SRAM column decoder22.

[Array Arrangement 3]

FIG. 10 shows a layout of an array in a semiconductor memory device inaccordance with another embodiment of the present invention. A CDRAMshown in FIG. 10 includes a 4M bit DRAM array and a 16K bit SRAM array.More specifically, the CDRAM of FIG. 10 includes 4 CDRAMs shown in FIGS.7 or 9. Referring to FIG. 10, the CDRAM includes four memory mats MM1,MM2, MM3 and MM4 each having the storage capacity of 1M bit. Each of theDRAM memory mats MM1 to MM4 includes a memory cell arrangement of 1024rows (word lines) by 512 columns (bit line pairs). Each of the DRAMmemory mats MM1 to ME4 is divided into 32 memory blocks MBs each havinga structure of 128 columns (bit line pairs)×256 rows (word lines).

One memory mat MM is divided into 4 memory blocks in the row direction,and into 8 blocks in the column direction. As shown in FIG. 10, a 1M bitmemory mat is divided into 8 blocks in the column direction and 4 blocksin the row direction, different from the arrangement of the DRAM of FIG.7, in order to house the device in a rectangular package, as will bedescribed later.

Sense amplifiers DSA for DRAMs and column selecting gates CSG arearranged corresponding to respective bit line pairs DBL at the centralportion in the column direction of the respective memory blocks MB. Amemory block MB is divided into an upper memory block UMB and a lowermemory block LMB with the sense amplifier DSA and column selecting gateCSG positioned at the center. In operation, either the upper memoryblock UMB or the lower memory block LMB is connected to the senseamplifier DSA and to the column selecting gate CSG. Whether the uppermemory block UMB or lower memory block LMB is to be connected to senseamplifier DSA and column selecting gate CSG is determined by an address.Such a structure in which one memory block MB is divided into upper andlower two memory blocks UMB and LMB and one of the two blocks isconnected to sense amplifier DSA and to column selecting gate CSG iscommonly used in DRAMs having shared sense amplifier structure havingthe storage capacity equal to or larger than 4M bit.

One memory mat MM includes two activation sections AS. One word line isselected in one activation section. Different from the structure shownin FIG. 7, one word line is divided into two portions and allotted torespective activation sections in the structure of FIG. 10. Namely,selection of one word line in one memory mat MM is equivalent toselection of one word line in each activation section AS.

The semiconductor device (CDRAM) further comprises 4 DRAM row decodersDRD1, DRD2, DRD3 and DRD4 for selecting one word line from each of fourDRAM memory mats MM1 to MM4. Therefore, in the CDRAM shown in FIG. 10, 4word lines are selected at one time. DRAM row decoder DRD1 selects onerow from corresponding activation sections AS of the memory mats MM1 andMM2. DRAM row decoder DRD2 selects one row from lower activationsections AS of memory mats MM1 and MM2. DRAM row decoders DRD3 and DRD4select one row from upper activation sections AS of DRAM memory mats MM3and MM4 and from lower activation sections AS of this memory mat,respectively.

The CDRAM further comprises DRAM column decoders DCD for selecting twocolumns (bit line pairs) from each of the column blocks of memory matsMM1 to MM4 of the DRAM. Column selection signal from the DARM Columndecoder DCD is transmitted to a column selection line CSL shown in FIG.8. A column selection line CSL extends to be shared by the upper andlower activation sections AS. Therefore, in the structure shown in FIG.10, 4 columns are selected from one column block (in FIG. 10, a blockincluding 8 memory blocks MBs divided in the column direction), by thecolumn selection signal from DRAM column decoder DCD.

Columns selected by column decoder DCD are connected to correspondingglobal I/O line pairs GIO. Two pairs of global I/O lines GIO extend inthe column direction in each column block in one activation section.Connection between the global I/O line pair GIO and local I/O line pairLIO in each column block will be described in detail later.

CDRAM shown in FIG. 10 further includes SRAM array blocks SMA1 to SMA4each formed of SRAM cells having the capacity of 4K bit. Row decodersSRD1 and SRD2 for SRAM are provided at a middle portion between 2 SRAMarray blocks to be shared by two SRAM array blocks. SRAM row decoderSRD1 is commonly used by SRAM array blocks SMA1 and SMA3. SRAM rowdecoder SRD2 is commonly used by SRAM array blocks SMA2 and SMA4.Details of the structure of SRAM array block SMAwill be described indetail later.

The CDRAM includes 4 input/output buffer circuits IOB1, IOB2, IOB3 andIOB4 for carrying out input/output of data 4 bits by 4 bits.Input/output buffer circuits IOB1 to IOB4 are connected to blocks SCDAof sense amplifiers and column decoders for SRAM, through common databuses (internal data buses), respectively. In the structure shown inFIG. 10, input/output of data are shown to be carried out through thesense amplifier and column decoder block SCDA for the SRAM. However,input/output of data may be carried out through the portion ofbi-directional transfer gates BTG.

In operation, one word line is selected in each activation section AS.Only the row block including the selected word line is activated. Otherrow blocks are maintained at the precharge state. In the selected rowblock, only a small block UMB (or LMB) including the selected word lineis connected to the sense amplifier DSA and column selecting gate CSGfor DRAM, and the other small memory block LMB (or UMB) in the selectedblock is separated from sense amplifier DSA and column selecting gateCSG for DRAM. Therefore, as a whole, activation (charge/discharge) of1/8 of bit lines is effected. By this partial activation, powerconsumption in charging/discharging of the bit lines can be reduced. Inaddition, by dividing one memory block MB into an upper memory block UMBand a lower memory block LMB and by arranging a sense amplifier DSA atthe center therebetween, the bit line can be made shorter, the ratioCb/Cs of bit line capacitance Cb to memory capacitor capacitance Cs canbe reduced, and sufficient reading voltage can be obtained at highspeed.

In each activation section AS, sensing operation in 4 small blocks UMB(or LMB) in the row direction is carried out. In each activation sectionAS, two pairs of bit lines are selected in one column block by a columnselection signal from DRAM column decoder DCD. Global I/O line pair GIOextends in the column direction to be shared by column blocks in eachactivation section AS. Two pairs of bit lines are selected from eachcolumn block in each activation section AS and connected tocorresponding two pairs of global I/O lines GIO. 4 pairs of global I/Olines GIO are connected to one bi-directional transfer gate BTG. 4bi-directional transfer gates BTG are provided for one memory mat MM.Therefore, 16 pairs of global I/O lines GIO can be connected to SRAM bitline pairs SBL of the corresponding SRAM array from one memory mat MM.Layout of the global I/O lines will be described.

FIG. 11 shows arrangement of global I/O lines for one memory mat.Referring to FIG. 11, the global I/O line pair GIO includes an upperglobal I/O line pair UGIO provided for an upper activation section UASand a lower global I/O line pair LGIO provided for a lower activationsection LAS. The upper global I/O line pair UGIO and the lower globalI/O line pair LGIO are arranged in parallel. Lower global I/O line pairGIO passes through upper activation section UAS but is not connected tolocal I/O line pair LIO in the upper activation section UAS. Global I/Oline pair GIO and local I/O line pair LIO are connected through an IOgate IOG which is a block selecting switch. Only an IO gate IOG providedin the row block including the selected word line is turned on by ablock selecting signal φBA and connects the corresponding local I/O linepair LIO to the corresponding global I/O line pair GIO.

Since DRAM sense amplifier DSA and column selecting gate CSG arearranged at the central portion in the column direction of the memoryblock MB, local I/O line pair LIO is arranged along the row direction atthe central portion in the column direction of memory block MB.

A word line shunt region WSR is provided in the column direction betweenadjacent column blocks. A word line shunt region WSR is used to providea contact between a word line formed of polysilicon having relativelyhigh resistance and an aluminum interconnection having low resistance.The word line shunt region will be described briefly.

FIG. 12 schematically shows a cross sectional structure of a selectingtransistor Q0 (see FIG. 11) included in a DRAM cell. Referring to FIG.12, the selecting transistor Q0 includes impurity regions IPR formed ata surface of a semiconductor substrate SUB, a bit line BL connected toone impurity region IPR, and a polysilicon layer PL formed on thesurface of the semiconductor substrate between the two impurity regionsIPR. When a word line driving signal DWL (the signal line and the signaltransmitted thereon are represented by the same reference character) istransmitted to the polysilicon layer PL, a channel is formed at thesurface of the semiconductor substrate between the impurity regions IPR,and the selecting transistor Q0 is turned on. Polysilicon has relativelyhigh resistance. If word line DWL has high resistance, a signal delay isgenerated due to the resistance of polysilicon. In order to lower theresistance of the word line DWL, an aluminum interconnection AL havinglow resistance is provided in parallel to the polysilicon layer PL. Byperiodically connecting the aluminum interconnection AL and thepolysilicon layer PL at predetermined intervals, the resistance of theword line DWL can be reduced. Aluminum interconnection AL is formedabove the bit line BL. Therefore, a region for providing contact betweenpolysilicon layer PL and aluminum interconnection AL must be provided ata region where there is no bit line BL (/BL), that is, a region wherememory cell is not arranged. For this purpose, a word line shunt regionis provided between cole blocks. The manner of connection is shown inFIG. 13.

Referring to FIG. 13, aluminum interconnection AL having low resistanceis provided in parallel to polysilicon layer PL having relatively highresistance serving as a word line. Word line driving signal DWL istransmitted to aluminum interconnection AL. Aluminum interconnection ALand polysilicon layer PL are periodically connected to each other by acontact layer CNT in word line shunt region WSR. By periodicallyproviding contacts between aluminum interconnection AL and polysiliconlayer PL through contact region CNT, the resistance of polysilicon layerPL can be effectively reduced. Therefore, even if a word line is verylong, the word line driving signal WL can be transmitted to the terminalend of the word line at high speed.

FIG. 14 schematically shows a layout of global I/O lines and columnselecting lines CSL. In FIG. 14, layout of these lines for two memoryblocks MB only is shown. In FIG. 14, global I/O line pair GIO isarranged in word line shunt region WSR. DRAM word lines DWL are arrangedin a direction orthogonally crossing the global I/O line pair GIO. InFIG. 14, aluminum interconnection AL and polysilicon layer are arrangedin parallel to each other, and in this plan view, they are overlappedwith each other. Therefore, they are shown as the same word lines DWL.Column selecting lines CSL for transmitting column selection signal fromDRAM column decoder are arranged in a direction orthogonally crossingDRAM word lines DWL.

Although the bit line pairs DBL of DRAM are not shown in this layout,the bit line pairs are arranged in parallel to column selecting linesCSL. Aluminum interconnection AL (see FIG. 12) for DRAM word lines DWLis formed by a first layer aluminum interconnection. Column selectinglines CSL are formed by a second layer aluminum interconnection. GlobalI/O lines are formed by the same aluminum interconnection as the columnselecting lines CSL. By providing global I/O line pair GIO in word lineshunt region WSR, chip area is not increased even if I/O lines forconnecting DRAM array and bi-directional transfer gates are adapted tohave hierarchical structure of local I/O lines and global I/O lines.

FIG. 15 schematically shows a structure of SRAM array block SMA shown inFIG. 10. Referring to FIG. 15, a SRAM array block SMA includes 16 pairsof bit lines SBL and 256 SRAM word lines SWL. SRAM cells SMC arearranged at crossings of SRAM bit line pairs SBL and SRAM word linesSWL. As shown in FIG. 10, in order to have the SRAM array block SMAaccordant with a rectangular chip layout, SRAM bit line pairs SBL arearranged in the row direction of DRAM array and SRAM word lines SWL arearranged in column direction of DRAM array. SRAM word lines SWL areconnected to SRAM row decoder SRD.

SRAM bit line pairs SBL must be connected to global I/O line pair GIOthrough bi-directional transfer gate BTG. Therefore, SRAM bit line pairsSBL must be connected to bi-directional transfer gate BTG on the lowerside as viewed in FIG. 15 (or upper side of FIG. 15: determined by thearrangement of the memory array). For this purpose, in the structureshown in FIG. 15, SRAM bit line taking lines SBLT are arranged inparallel to SRAM word lines SWL.

The number of SRAM bit line taking lines SBLT is the same as the numberof bit line pairs SBL of the SRAM array block SMA, and the taking linesare connected to corresponding SRAM bit line pairs SBL. If SRAM bit linetaking lines SBLT are formed by the same interconnection layer as SRAMword lines SWL, SRAM bit line taking lines SBLT can be implementedeasily without additionally providing interconnection layers formed byadditional step of manufacturing.

The SRAM row decoder SRD decodes a row address for SRAM to select one ofthe 256 SRAM word lines SWL. 16 bits of SRAM cells SMC connected to theselected SRAM word line SWL are connected to corresponding SRAM bit linepair SBL and to SRAM bit line taking line SBLT. In data transfer, thebit line taking lines SBLT are connected to global I/O line pair GIOthrough bi-directional transfer gate BTG.

By employing such a layout as shown in FIGS. 11 and 15, a structure asshown in FIG. 10 can be realized, in which DRAM arrays are arrangeddivided into upper and lower portions as viewed in the figure, SRAMarrays are collectively arranged between the upper and lower DRAM arrayblocks, and input/output buffer circuits IOB1 to IOB4 are provided nearSRAM arrays formed at the central portion of the semiconductor memorydevice (chip). Such structure having SRAM arrays collectively formed atthe central portion of the chip and input/output of data are effectednear the central portion of the chip is advantageous for CDRAM as willbe described in the following.

High speed access to a cache register is the first and most importantcharacteristic of CDRAM. Arrangement of the SRAM array serving as thecache register near the input/output buffer for inputting/outputtingdata to and from the outside of the device results in shorter signallines, which enables high speed input/output of data, and thus meets thedemand of high speed accessing.

By collectively arranging SRAM arrays at the central portion, addresslines for selecting SRAM cells can be made shorter. If an address lineis made shorter, interconnection resistance and parasitic resistance ofthe address line can be reduced, SRAM cells can be selected at highspeed, and therefore it is suitable for high speed accessing to thecache register.

In the architecture shown in FIG. 10, interconnections connecting theDRAM array and SRAM array may be longer, lowering the speed of datatransfer between the DRAM array and SRAM array. However, data transferis carried out between DRAM array and SRAM array only when a cache miss(miss hit) occurs. In that case, access speed as low as that of thestandard DRAM is sufficient, and it is not very much desired to increasethis access speed. Therefore, this is not a problem in practical use. Inthis case also, writing/reading of data can be carried out at high speedby using the data transfer apparatus which will be described later.

[Another Arrangement of SRAM Array]

In this section, reference is made on FIGS. 16 to 30. SRAM array isarranged to implement any shape with storage capacity fixed. Each row ofSRAM array has a plurality of word lines associated therewith. One ofword lines is selected. One row corresponds effectively to a pluralityof rows. Data transfer between DRAM array and SRAM array of multiplicateword line arrangement be also described.

FIG. 16 shows a structure of the SRAM cell. Referring to FIG. 16, theSRAM cell SMC includes MOS (insulated gate type) transistors SQ1, SQ2,SQ3 and SQ4 constituting an inverter latch. P channel MOS transistor SQ1and n channel MOS transistor SQ3 are complementary connected betweenoperational supply potential Vcc and the other supply potential (groundpotential), forming one inverter circuit.

P channel MOS transistor SQ2 and n channel MOS transistor SQ4 arecomplementary connected between the operational supply potential Vcc andthe ground potential, forming the other inverter circuit. TransistorsSQ1 and SQ3 have their gates connected to an node SN1, and transistorsSQ2 and SQ4 have their gates connected to an node SN2. Node SN1 is anoutput node of one inverter circuit (transistors SQ1 and SQ3), and nodeSN2 is an output node of the other inverter circuit (transistors SQ2 andSQ4).

SRAM cell SMC further includes n channel MOS transistors SQ5 and SQ6rendered conductive in response to a signal on SRAM word line SWL forconnecting nodes SN1 and SN2 to bit lines SBL and *SBL. Diode connectedn channel MOS transistors SQ7 and SQ8 are provided on bit lines SBL and*SBL. MOS transistors SQ7 and SQ8 clamp the potential of "H" on bitlines SBL and *SBL at a potential Vcc-Vth and "L" thereon at VL1(described later). The character Vth represents the threshold voltage ofthe transistors SQ7 and SQ8.

Data writing and reading operations of the SRAM cell will be brieflydescribed.

In data writing, data complementary to each other are transmitted to bitline SBL and complementary bit line *SBL. Assume that a potential at "H"is transmitted to bit line SBL and a potential at "L" is transmitted tocomplementary bit line *SBL. Potential on word line SWL is at "H" andnodes SN1 and SN2 are connected to bit lines SBL and *SBL throughconductive transistors SQ5 and SQ6, respectively. The potential of nodeSN1 is applied to the gates of transistors SQ2 and SQ4, so thattransistor SQ4 is rendered conductive and transistor SQ2 is renderednon-conductive. The potential at "L" on node SN2 is applied to the gatesof transistors SQ1 and SQ3, so that transistor SQ1 is renderedconductive, and transistor SQ3 is rendered non-conductive. Consequently,the potential at node SN1 is set to "H", the potential on node SN2 isset to "L" and these potentials are latched by the inverter latchcircuits formed of transistors SQ1 to SQ4. By the fall of the potentialon SRAM word line SWL to "L", writing of data is completed.

In data reading, the potential of the SRAM word line SWL rises to "H"and transistors SQ5 and SQ6 are rendered conductive. The stored data(potential) which has been latched at nodes SN1 and SN2 are transmittedto bit lines SBL and *SBL, respectively. Complementary data of "H" and"L" are transmitted to bit lines SBL and *SBL. The signal potentials onbit lines SBL and *SBL are amplified by a sense amplifier, not shown,and thus data is read out .

FIG. 17 is a diagram for illustrating the functions of transistors SQ7and SQ8 shown in FIG. 16. The operation of the transistors SQ7 and SQ8will be described with reference to FIGS. 16 and 17.

Transistors SQ7 and SQ8 are diode connected, and clamp the potentials onbit lines SBL and *SBL to Vcc-Vth. More specifically, the "H" potentiallevel of the potential amplitude of bit lines SBL and *SBL is set toVcc-Vth. The data of "H" latched in node SN1 has the potential at Vcclevel. When the latched data of "H" is transmitted to bit line SBL, thelevel of this data attains Vcc-Vth, because of signal loss by transistorSQ5.

The "L" levei potential VL1 of the potential amplitude of bit line SBL(or *SBL) is determined by resistive division of transistors SQ4, SQ6and SQ8 (or SQ3, SQ5 and SQ7). The potential VL1 of "L" level of the bitline potential amplitude is higher than the ground potential Vss.

Namely, transistors SQ7 and SQ8 have also a function of raisingpotential of "L" of bit lines SBL and *SBL.

Assume that transistors SQ7 and SQ8 are not provided. In that case, the"L" level potential VL2 of bit lines SBL and *SBL are discharged bytransistors SQ6 and SQ4 (or SQ5 and SQ3) to the ground potential Vss tobe approximately at the ground potential level. The "H" level potentialof bit line SBL (or *SBL) is provided as Vcc-Vth even when transistorsSQ7 and SQ8 are not provided. In this case, it is assumed that the "H"level applied to word line SWL is at the level of operational supplyvoltage Vcc, and that there is a loss of the threshold voltage Vth oftransistor SQ5 or SQ6 in transistor SQ5 (or SQ6).

Assume that the potential on SRAM word line SWL rises to "H" at time TWLin FIG. 17. When transistors SQ7 and SQ8 are provided, data stored inSRAM cell SMC is transmitted to bit lines SBL and *SBL, and potentialsand "L" on bit lines SBL and *SBL cross at time T1.

When transistors SQ7 and SQ8 are not provided, the potentials "H" and"L" of bit lines SBL and *SBL cross at time T2.

Data on respective bit lines SBL and *SBL are established after the timeof crossing of potentials "H" and "L" on bit lines SBL and *SBL.Therefore, by the provision of transistors SQ7 and SQ8, logic amplitudeof bit lines SBL and *SBL can be made smaller and the access time can bemade shorter.

Different from the DRAM, the SRAM does not need RAS precharge time, andtherefore it can be accessed at high speed. However, in SRAM array, onememory cell always exists at a crossing of an SRAM word line and a bitline. One memory cell is connected to bit line SBL and complementary bitline *SBL. A SRAM cell includes 6 transistors as shown in FIG. 16, andtherefore compared with a DRAM cell including one transistor and onecapacitor, it occupies larger area. Therefore, to provide a CDRAM whichis highly integrated with high density, SRAM array should be effectivelyarranged in as small an area as possible.

Assume that the CDRAM is to be housed in a rectangular package 550 asshown in FIG. 18. Package 550 has a longer side direction represented byX and a shorter side direction represented by Y in FIG. 18. Forpackaging in such a rectangular package, a DRAM array 560 having largestorage capacity is arranged in a rectangular so as to match with theshape of package (or chip) 550. Here, it should be noted that the chiphaving DRAM array and CDRAM array integrated thereon has the same shapeas the package. Data are transferred bi-directionally through transfergate 570 between DRAM array 560 and SRAM array 580. In such arrangement,the SRAM array 580 should have the same length as the shorter sidelength of the DRAM array, in view of effective chip area occupation orarray layout.

Assume that DRAM array 560 and SRAM array 580 can transfer data of 16bits at one time, as shown in FIG. 19 and described previously. In thiscase, cache size is 16 bit. 16 pairs of SRAM bit lines SBL and *SBL arearranged for one SRAM word line SWL. SRAM array 580 has a structure of256 rows×16 columns. When 256 SRAM word lines SWL1 to SWL256 arearranged along the longer side of package 550 as shown in FIG. 19, SRAMarray 580 becomes long in the long side direction (X direction). If so,it can not be arranged in the area allotted to SRAM array 580 of package550.

If SRAM word lines SWL1 to SWL256 are arranged in the short sidedirection (Y direction) of package 550 as shown in FIG. 20, the lengthin the long side direction (X direction) in FIG. 18 can be reduced, butit becomes longer in the short side direction (Y direction). Therefore,in this case also, it can not be arranged in the area allotted to SRAMarray in package 550.

The size of SRAM array is determined uniquely when the number of bitline pairs and the number of SRAM word lines are determined. Therefore,the shape of SRAM array can not be flexibly changed.

In SRAM array, when a memory cell is selected, current always flowsthrough the selected memory cell. Therefore, in view of currentconsumption, the number of memory cells connected to one word lineshould preferably be as small as possible. If the number of word linesare increased to reduce the number of memory cells connected to one wordline, the bit line becomes longer. This in turn causes a problem thatparasitic capacitance of the bit line is increased and access time isincreased.

The shape of the DRAM array can be changed to be suited for the packagerelatively easily, by employing block divided arrangement, shared senseamplifier structure and the like. Therefore, it is preferred to providea semiconductor memory device containing a cache occupying small area torealize an SRAM array structure whose shape can be flexibly changedcorresponding to the shape of the DRAM array.

The arrangement of the DRAM array and the SRAM array in the rectangulararea as described previously is required to house a 4M CDRAM in arectangular package. The SRAM array SMA is arranged between DRAM arraysMMs as shown in FIG. 10. SRAM array SMA is arranged in a rectangularregion which is short in the long side direction (X direction) of thechip and long in the short side direction (Y direction) of the chip.

SRAM array SMA has a storage capacity of 4K bits, and transfers 16 bitsof data at one time to and from the corresponding DRAM array MM througha bi-directional transfer gate circuit BTG.

In this embodiment, SRAM array SMA includes 256 word lines and 16 pairsof bit lines. The SRAM array structure for effectively arranging SRAMarray in the rectangular area will be described.

FIG. 21 shows in principle the structure of the SRAM array in accordancewith an embodiment of the present invention. FIG. 21 shows two SRAM wordlines SWL1 and SWL2 and two pairs of bit lines SBL1, *SBL1, SBL2 and*SBL2, as representatives. SRAM cells SMC1 and SMC2 are arranged in onerow. SRAM word lines SWL1 and SWL2 are commonly provided for the row inwhich SMC1 and SMC2 are arranged. Word line SWL1 is connected to memorycell SMC1. Word line SWL2 is connected to memory cell SMC2. SRAM memorycell SMC1 is connected to bit line pair SBL1, *SBL1. Memory cell SMC2 isconnected to bit line pair SBL2, *SBL2.

Clamping transistors SQ7, SQ8, SQ15 and SQ16 are provided for clamping"H" and "L" level potential of the bit line potential for bit linesSBL1, *SBL1, SBL2 and *SBL2. Memory cells SMC1 and SMC2 have the samestructure as the SRAM cell SMC shown in FIG. 16 and has a structure of alatch type storing element. SRAM cell SMC1 includes p channel MOStransistors SQ1 and SQ2 and n channel MOS transistors SQ3, SQ4, SQ5 andSQ6. Transistors SQ5 and SQ6 are rendered conductive in response to asignal potential on word line SWL1 and connect nodes SN1 and SN2 to bitlines SBL1 and *SBL1, respectively. Transistors SQ1, SQ2, SQ3 and SQ4constitute an inverter type latch circuit.

SRAM cell SMC2 includes p channel MOS transistors SQ9 and SQ10 and nchannel MOS transistors SQ11, SQ12, SQ13 and SQ14. Transistors SQ13 andSQ14 are rendered conductive in response to a signal potential on SRAMword line SWL2, and connect nodes SN3 and SN4 to bit lines SBL2 and*SBL2. Transistor SQ9, SQ10, SQ11 and SQ12 constitute an inverter typelatch circuit.

In the array arrangement shown in FIG. 21, memory cells existing on evennumbered columns (SMC2 and the like) of memory cells arranged in one roware connected to word line SWL2, while memory cells existing on oddnumbered columns (SMC1 and the like) are connected to word line SWL1.The number of memory cells connected to word line SWL1 is the same asthe number of memory cells connected to the word line SWL2. In thisstructure, an SRAM array having an arbitrary shape can be easilyrealized, as will be made clear later.

FIGS. 22A and 22B shows a comparison between the conventional SRAM arrayarrangement and the SRAM array arrangement of the present invention.Referring to FIG. 22A, one word line SWL is arranged for one row ofmemory cells. In this case, memory cells SMCs are arranged in M rows×Ncolumns.

Meanwhile, as shown in FIG. 22B, two word lines SWLa and SWLb areprovided for one row of memory cells SMC, and one row of memory cellsSMCs are connected alternately to word lines SWLa and SWLb. In thiscase, memory cells SMCs are arranged in M/2 rows×2N columns. In botharray arrangements shown in FIGS. 22A and 22B, N memory cells SMCs areconnected to one word line. In the structure of FIG. 22B, when three ormore word lines are arranged for one row of memory cells and memorycells are connected alternatively to respective word lines, an SRAMarray having an arbitrary shape can be provided. This increases degreeof freedom in designing the structure and arrangement of the SRAM arrayin chip lay out.

FIG. 23 shows a pattern of memory cell arrangement shown in FIG. 21. Thestructure of the memory cell will be described briefly with reference toFIG. 23. Supply line Vcc, SRAM word lines SWL1 and SW2 and a ground lineGND are arranged in parallel and formed by a second layer aluminuminterconnection (second aluminum interconnection). Bit lines SBL1,*SBL1, SBL2 and *SBL2 are formed by a first layer aluminuminterconnection (first aluminum interconnection). Gates of transistorsSQ1 to SQ16 are formed by a first layer polysilicon interconnection(first poly interconnection). The respective transistors are connectedby a fourth layer polysilicon interconnection (fourth polyinterconnection), and word lines are connected to the gates of thetransistors by the first layer aluminum interconnection. Memory cellsSMC1 and SMC2 have the same pattern layout. In the following, connectionof memory cell SMC1 will be described.

Clamping transistor SQ7 has its drain connected to bit line SBL1 througha contact hole CX1, its gate and source connected to the first layeraluminum interconnection through contact holes CX3 and CX2, and thisfirst aluminum interconnection is connected to supply line Vcc through acontact hole CX6. Transistor SQ8 has its drain connected to bit line*SBL1 formed of the first layer aluminum interconnection through acontact hole CX5, and its gate and source connected to the first layeraluminum interconnection layer through contact holes CX4 and CX2, andthis first layer aluminum interconnection layer is connected to supplyline Vcc through contact hole CX6.

Transistor SQ1 has its drain connected to the first layer aluminuminterconnection through a contact hole CX8, and this first layeraluminum interconnection is connected to the fourth layer polysiliconinterconnection through a contact hole CX9. This fourth layerpolysilicon interconnection connected to contact hole CX9 provides nodeSN1. Node SN1 is connected to gate electrodes of transistors SQ2 and SQ4through the fourth layer polysilicon interconnection and contact holeCX11. This fourth layer polysilicon interconnection of node SN1 isconnected to the drain of transistor SQ3 and to one conduction terminalof transistor SQ5 through contact hole CX16.

Transistor SQ1 has its gate connected to node SN2 through contact holeCX10 and through the fourth layer polysilicon interconnection.Transistor SQ1 has its source connected to supply line Vcc throughcontact hole CX7, the first layer aluminum interconnection and contacthole CX6.

Transistor SQ2 has its drain connected to the first layer aluminuminterconnection through a contact hole CX23, and this first layeraluminum interconnection is connected to the fourth layer polysiliconinterconnection through a contact hole CX22. The fourth layerpolysilicon interconnection connected to contact hole CX22 provides nodeSN2. Transistor SQ1 has its gate connected to the fourth layerpolysilicon interconnection providing node SN1, through contact holeCX11.

Transistor SQ3 has its drain connected to the fourth layer polysiliconinterconnection through contact hole CX16 and connected to node SN1.Transistor SQ3 has its gate connected to the fourth polysiliconinterconnection layer through contact hole CX10 and to node SN2.

Transistor SQ3 has its source connected to the first layer aluminuminterconnection through contact hole CX18, and the first layer aluminuminterconnection is connected to the ground line GND through contact holeCX17.

Transistor SQ4 has its source connected to ground line GND throughcontact hole CX18, the first layer aluminum interconnection and contacthole CX17. Transistor SQ4 has its gate connected to node SN1 throughcontact hole CXll and the fourth layer polysilicon interconnection.Transistor SQ4 has its drain connected to node SN2 through contact holeCX20 and the fourth layer polysilicon interconnection.

Transistor SQ5 has its gate connected to the first layer aluminuminterconnection through contact hole CX14, and this first aluminuminterconnection is connected to word line SWL1 through contact holeCX12.

Transistor SQ6 has its gate connected to the first layer aluminuminterconnection through contact hole CX19, and to word line SWL1 throughcontract hole SX12. One conduction terminal of transistor SQ6 isconnected to bit line SBL1 through contact hole CX21. The otherconduction. terminal of transistor SQ6 is connected to node SN2 throughcontact hole CX20 and the fourth layer polysilicon interconnection.

As shown in FIG. 23, memory cells are arranged in one row, two wordlines SWL1 and SWL2 can be arranged for the one row, and multiplicateword line arrangement in which a plurality of word lines are providedfor memory cells arranged in one row can be easily realized.

FIG. 24 shows an SRAM array arrangement in accordance with oneembodiment of the present invention. The SRAM array arrangement shown inFIG. 24 is applied to the 4K bit SRAM array shown in FIG. 10. Referringto FIG. 24, the SRAM array SMA includes static memory cells (SRAM cells)arranged in 128 rows and 32 columns. Two SRAM word lines SWL areprovided for SRAM cells arranged in one row. For example, two SRAM wordlines SWL1 and SWL2 are provided for the first row of SRAM cells. SRAMword lines SWL3 and SWL4 are provided for the second row of memorycells.

SRAM cells of the odd numbered columns are connected to odd numberedSRAM word lines (SWL1, SWL3, . . . ) while SRAM cells of the evennumbered columns are connected to even numbered SRAM word lines (SWL2,SWL4, . . . ). Every other SRAM cells of the respective rows of SRAMcells are connected to corresponding SRAM word lines SWL1 to SWL256.Namely, 16 bits of SRAM cells are connected to each of SRAM word linesSWL1 to SWL256.

In accessing SRAM cell, a column should be selected. The arrangement ofFIG. 24 includes effectively 16 columns. In column selection, SRAMcolumn address and word line group designating signal (a leastsignificant SRAM row address bit, for example) are combined to generatea SRAM column select signal to connect a selected SRAM column tointernal data bus.

As shown in FIG. 10, an SRAM row decoder for selecting the SRAM wordlines is arranged in a direction orthogonally crossing the word linesSWL1 to SWL256. Data is transferred between the DRAM array and a SRAMcell through a transfer gate circuit BTG. Data must be transferredthrough SRAM bit lines SBL and *SBL. Therefore, as in the case of FIG.15, bit line taking line SBLT is provided for each bit line pair SBL and*SBL. The bit line taking lines SBLT and *SBLT are formed by the secondlayer aluminum interconnection.

One bi-directional transfer gate circuit BTG is provided for two pairsof bit lines SBL and *SBL, that is, two pairs of SRAM bit line takinglines SBLT and *SBLT. Bi-directional transfer gate circuit BTG isconnected to corresponding global I/O lines GIO and *GIO. 16 bits ofdata are transferred at one time between DRAM array and SRAM arraythrough bi-directional transfer gate 210. In accordance with thestructure, one transfer gate circuit can be arranged for two pairs ofSRAM bit line taking lines SBLT and *SBLT in the SRAM array.Consequently, pitch condition in the Y direction for transfer gatecircuit BTG can be released, and therefore even a transfer gate circuithaving a complicated structure can be formed with sufficient margin.

Although memory cells are arranged in 128 rows and 32 columns in thearrangement of SRAM array shown in FIG. 24, the structure issubstantially equivalent with the SRAM array of 256 rows×16 columns. Inthis case, the dimension in Y direction can be reduced to approximatelyone half of the SRAM array arrangement of 256 rows×16 columns, andtherefore SRAM cells can be arranged in the rectangular SRAM array areashown in FIGS. 10 or 18. In the SRAM array arrangement shown in FIG. 24,only one half of memory cells of one row of memory cells are selected,which realizes substantial block dividing operation or partialactivation, and thus the SRAM can be driven with low currentconsumption.

Now, data transfer between DRAM array of FIG. 8 and SRAM array of FIG.24 will be described with reference to FIGS. 25 through 30.

FIG. 25 shows an example of the structure of the transfer gate circuitBTG shown in FIG. 24. FIG. 25 shows, as a representative, a transfergate circuit BTG1 provided for SRAM bit line pairs SBL1, *SBL1 and SBL2and *SBL2, that is, for SRAM bit line taking lines SBLT1, *SBLT1, SBLT2and *SBLT2. Transfer gate circuit BTG includes a selecting circuit 9501for selecting a pair of bit lines out of two pairs of bit lines inresponse to an address signal Acd for the SRAM; and a transfer circuit9502 for connecting global I/O lines GIO1 and *GIO1 to internal nodes Aand B for transferring data between nodes A and B and global I/O linesGIO1 and *GIO1.

The least significant bit of the row address for the SRAM is used as theselection control signal applied to the selecting circuit 9501. Whenselected SRAM word line is an even numbered word line, selecting circuit9501 selects SRAM bit line taking lines SBLT1 and *SBLT1 correspondingto the even numbered colE, and otherwise it selects SRAM bit line takinglines SBLT2 and *SBLT2 corresponding to the odd numbered column.

The details of the structure of transfer circuit 9502 will be describedlater. Any circuit having the function of bi-directional data transfermay be used.

FIG. 26 shows an example of a specific structure of selecting circuit9501 shown in FIG. 25. Referring to FIG. 26, selecting circuit 9501includes an n channel MOS transistor GTr1 responsive to a selectioncontrol signal Acd for selecting SRAM bit line taking line SBLT1 (or*SBLT1), and a p channel MOS transistor GTr2 responsive to the selectioncontrol signal Acd for selecting SRAM bit line taking line SBLT2 (or*SBLT2). The other terminal of each of the transistors GTr1 and GTr2 isconnected to node A (or B).

In the structure shown in FIG. 26, when selection control signal Acd is1 ("H" level), transistor GTr1 is rendered conductive, and SRAM bit linetaking line SBLT1 (or *SBLT1) is selected and connected to node A (orB). When selection control signal Acd is 0 ("L" level), SRAM bit linetaking line SBLT2 (or *SBLT2) is selected and connected to node A (orB).

In the structure shown in FIG. 24, clamp transistors (indicated by theblock CLP) for raising "L" level of potential amplitude are provided forthe SRAM bit line pair SBL and *SBL. Therefore, the non-selected bitline pairs are maintained at the "H" clamp potential, and potential ofeach bit line changes only for the selected columns.

In the SRAM array structure shown in FIG. 24, the clamp transistor(represented by block CLP in FIG. 24) provided for each SRAM bit linepair SBL, *SBL are always kept conductive. A structure in which functionof the clamp transistor is stopped during the SRAM word line selectingoperation may be used.

FIG. 27 shows another structure of the SRAM array and a structure of thebi-directional transfer gate circuit used associatively. FIG. 27 shows,as representatives, SRAM bit line pairs SBL0, *SBL0, SBL1 and *SBL1. TheSRAM cells are omitted for simplicity of the drawing. Accurately, SRAMbit line taking lines SBLT and *SBLT are connected to the transfer gatecircuit (BTG1). However, in FIG. 27, the SRAM bit lines SBL and *SBL areshown to be directly connected to the transfer gate circuit.

Referring to FIG. 27, for SRAM bit line pair SBL0 and *SBL0, p channelMOS transistors SQE1, SQE2 and SQE3 responsive to a SRAM bit lineequalizing signal SBLEQ for precharging and equalizing SRAM bit linesSBL0 and *SBL0 to a predetermined potential, and p channel MOStransistors SQC1 and SQC2 responsive to a SRAM bit line clamping signalSBLCL for clamping potentials on SRAM bit lines *SBL0 and SBL0 areprovided. Transistors SQE1 and SQE2 precharge SRAM bit lines *SBL0 andSBL0 to a predetermined potential (Vcc) in response to SRAM bit lineequalizing signal SBLEQ. Transistor SQE3 equalizes potential on SRAM bitlines SBL0 and *SBL0 in response to SRAM bit line equalizing signalSBLEQ.

Transistors SQC1 and SQC2 clamp potentials on SRAM bit lines *SBL0 andSBL0 in response to SRAM bit line clamping signal SBLCL. TransistorsSQC1 and SQC2 also function as load transistors. SRAM bit lineequalizing signal SBLEQ is generated at a standby of the SRAM, and SRAMbit line clamping signal SBLCL is set to the inactive state of "H" whena word line is selected in the SRAM array.

For SRAM bit lines *SBL1 and SBL1, p channel MOS transistors SQE4, SQE5and SQE6 which are rendered conductive in response to SRAM bit lineequalizing signal SBLEQ, and p channel MOS transistors SQC3 and SQC4which are rendered conductive in response to SRAM bit line clampingsignal SBLCL are provided. Transistors SQE4 and SQE5 precharge SRAM bitlines *SBL1 and SBL1 at the time of standby. Transistor SQE6 equalizespotentials on bit lines *SBL1 and SBL1 at the standby of the SRAM.Transistors SQC3 and SQC4 clamp potentials on SRAM bit lines *SBL1 andSBL1.

In the SRAM array arrangement shown in FIG. 27, each of the bit linesSBL and *SBL is precharged to the "H" level at the standby of the SRAM,the clamping transistor is rendered non-conductive only when the wordline is being selected, and SRAM bit lines are set to the floatingstate. In this state, when SRAM bit lines SBL0 and *SBL0 are selected,potential change corresponding to the data stored in the selected memorycell appears on the bit lines. Meanwhile, non-selected bit line pairSBL1 and *SBL1 is maintained at "H" level of the potential having beenclamped by the clamping transistors SQC3 and SQC4. In such a structurein which potentials of one pair of bit lines out of two pairs of bitlines connected to one transfer gate circuit is at the clamp potentialand potential change corresponding to the stored data of the memory cell(SRAM cell) appears only on the other bit line pair, selecting circuitfor selecting an SRAM bit line pair is not necessary when data istransferred from the SRAM array to the DRAM array.

The structure shown in FIG. 27 utilizes the fact that the potential ofone bit line pair is clamped at "H". Referring to FIG. 27, the transfergate circuit 9600 (BTG1) includes an amplifier 9601 receiving signalpotentials on SRAM bit line pairs SBL0, *SBL0 and SBL1, *SBL1 foramplifying potential of the SRAM bit lines on which potential change isgenerated; a first transfer circuit 9602 for transferring a signal fromamplifier 9601; a latch circuit 9603 for latching signal datatransferred from first transfer circuit 9602; and a second transfercircuit 9604 for transferring data latched in latch circuit 9603 to DRAMarray (global IO line). Amplifier 9601, first transfer circuit 9602,latch 9603 and second transfer circuit 9604 are used for data transferfrom SRAM array to DRAM array.

Bi-directional transfer gate circuit 9600 further includes an amplifier9605 for amplifying data from global IO lines GIO1 and *GIO1 from theDRAM array; a third transfer circuit 9606 for transferring dataamplified by amplifier 9605; and selecting gate 9607 for transmittingdata from transfer circuit 9606 by selecting corresponding SRAM bit linepair in accordance with the least significant bit Acdr of the SRAM rowaddress. Amplifier 9605, third transfer circuit 9606 and selecting gate9607 are used for data transfer from the DRAM array to the SRAM array.

FIG. 28 shows a specific structure of the data transfer path from theSRAM array to the DRAM array. Referring to FIG. 28, amplifier circuit9601 includes n channel MOS transistors SQA1 and SQA2 having their gatesconnected to SRAM bit lines SBL0 and SBL1, respectively; and n channelMOS transistors SQA3 and SQA4 having their gate connected to respectivecomplementary SRAM bit lines *SBL0 and *SBL1. Transistors SQA1 and SQA2are connected in series, and the other conduction terminal of transistorSQA2 is connected to ground potential Vss. Transistors SQA3 and SQA4 areconnected in series, and the other conduction terminal of transistorSQA4 is connected to ground potential Vss.

First transfer circuit 9602 includes n channel MOS transistors SQA5 andSQA6 which are rendered conductive in response to data transferdesignating signal DTL. Transistor SQA5 is connected in series withtransistor SQA1, and transistor SQA6 is connected in series withtransistor SQA3.

Latch circuit 9603 includes inverter circuits SIV1 and SIV2 connected inanti-parallel, and inverter circuits SIV3 and SIV4 for inverting datatransferred from transfer circuit 9602.

Second data transfer circuit 9604 includes a transfer gate 9604a fortransmitting an output from latch circuit 9603 to global I/O line GIO1,and a transfer gate 9604b for transferring data latched in latch circuit9603 to global I/O line *GIO1. Transfer gates 9604a and 9604b includes nchannel MOS transistors SQA7 and SQA8 which are rendered conductive inresponse to data transfer designating signal DTA, respectively.

FIG. 29 shows an example of the specific structures of the amplifier,the third transfer circuit and the selecting gate shown in FIG. 27.Referring to FIG. 29, amplifying circuit 9605 includes an n channel MOStransistor SQB1 having its gate connected to the global I/O line GIO1,an n channel MOS transistor SQB3 having its gate connected to thecomplementary global I/O line *GIO1, n channel MOS transistors SQB2 andSQB4 which are rendered conductive in response to data transferdesignating signal DTS for transmitting signal potential amplified bytransistors SQB1 and SQB3, and p channel MOS transistors SQB5, SQB6,SQB7 and SQB8 for amplifying and maintaining the signal potentialtransmitted from the transistors SQB2 and SQB4. Transistors SQB5 andSQB6 are connected in parallel between supply potential Vcc and nodeSND1. Data transfer designating signal DTS is applied to the gate oftransistor SQB6. The transistor SQB5 has its gate connected to nodeSND2. Transistors SQB7 and SQB8 are connected in parallel between supplypotential Vcc and node SND2. Transistor SQB7 has its gate connected tonode SND1. Data transfer designating signal DTS is applied to the gateof transistor SQB8.

Third transfer circuit 9606 includes two transfer gates 9606b and 9606a.Transfer gate 9606a includes an n channel MOS transistor SQB10 which isrendered conductive in response to data transfer designating signal DTSfor transmitting data amplified by amplifier circuit 9605. Transfer gate9606 includes an n channel MOS transistor SQB9 which is renderedconductive in response to data transfer designating signal DTS fortransmitting signal potential at node SND1 of amplifier circuit 9605.

Selecting gate 9607 includes two selecting gates 9607a and 9607b.Selecting gate 9607a includes an n channel MOS transistor SQB14 which isrendered conductive in response to SRAM address Acdr, and an n channelMOS transistor SQB13 which is rendered conductive in response to SRAMaddress *Acdr. The least significant bit (Ac4) of the row address of theSRAM array is used to generate the SRAM addresses Acdr and *Acdr.

Selecting gate 9607b includes an n channel MOS transistor SQB12 which isrendered conductive in response to address signal Acdr for transmittingdata from transfer gate 9606, and an n channel MOS transistor SQB11which is rendered conductive in response to complementary address signal*Acdr for transmitting data from transfer gate transistor SQB9. Whenaddress signal Acdr is at "H", transistors SQB12 and SQB14 are renderedconductive and bit line pair SBL1 and *SBL1 is selected. When addresssignal Acdr is at "L", transistors SQB11 and SQB13 are renderedconductive and bit line pair SBL0 and *SBL0 is selected.

Prior to the data transfer operation, the operation of the amplifiercircuit 9605 will be briefly described. Assume that global I/O line GIO1is at "H" and global I/O line *GIO1 is at "L". In this case, if thesignal DTS is at "H", transistor SQB1 is conductive and transistor SQB3is rendered non-conductive. Potential at node SND1 is discharged toground potential Vss, while there is no discharging path for thepotential at node SND2. In this case, transistor SQB7 is renderedconductive, and potential of node SND2 is charged by transistor SQB7.Therefore, the potential at node SND2 is set to "H" and potential atnode SND1 is set to "L". When data transfer is to be designated, datatransfer designating signal DTS rises to "H". Therefore, in datatransfer, transistors SQB6 and SQB8 are rendered non-conductive, andpotentials at nodes SND1 and SND2 are rapidly set at potentialscorresponding to the data which is to be transferred. Normally, thesignal DTS is at "L", and nodes SND1 and SND2 are maintained at "H"level by transistors SQB6 and SQB8. The data transfer operation of thetransfer circuit shown in FIG. 27 will be described with reference toFIG. 30, which is a diagram of signal waveforms.

In data transfer operation of transfer circuit 9600 shown in FIG. 27,data is transferred from the SRAM array to latch circuit 9603, whiledata is transferred from the DRAM array to the SRAM array. Thereafter,data which has been latched in latch circuit 9603 is transferred to DRAMarray. The data transfer operation of transfer circuit will be describedin detail later.

When SRAM bit line equalizing signal SBLEQ rises to "H", SRAM enters thememory cycle. In response, precharge and equalizing transistors SQE1 toSQE6 provided for each bit line pair SBL, *SBL are renderednon-conductive. At this time, SRAM bit line clamping signal SBLCL isstill at "L", and each bit line SBL, *SBL is maintained at "H" levelthrough the clamping transistors (SQC1, SQC2, SQC3 and SQC4).

Thereafter, word line selecting operation is executed in the SRAM array,and the SRAM word line rises. Approximately at the same time, the SRAMbit line clamping signal SBLCL rises to "H". Timing of rising ofclamping signal SBLCL may be set earlier than the word line selectingtiming in the SRAM array. Consequently, data of half of the memory cellsof one row are read. Assume that word line SWL1 is selected. In thiscase, referring to FIG. 27, SRAM bit line pair SBL0 and *SBL0 maintain"H" level as in the standby state. Meanwhile, potentials of SRAM bitline pair SBL1 and *SBL attain the levels corresponding to the datastored in the memory cells connected thereto. In this case, referring toFIG. 28, transistors SQA1 and SQA3 are rendered conductive.Conduction/non conduction of transistors SQA2 and SQA4 is determineddependent on the data of the selected memory cell at that time.

Responsive to the rise of data transfer designating signal DTL to "H",signal potentials on SRAM bit lines SBL1 and *SBL1 are latched by latchcircuit 9603.

In parallel to the latching operation, data transfer from the DRAM arrayto the SRAM array is executed. In the SRAM array, the word line is keptat the selected state. When signal potentials on global I/O lines GIO1and *GIO1 are established, conduction/non conduction of transistors SQB1and SQB3 is determined (see FIG. 29). Thereafter, when data transferdesignating signal DTS is generated, transistors SQB2 and SQB4 arerendered conductive, data on global I/O lines GIO1 and *GIO1 areinverted and amplified to be maintained at nodes SND1 and SND2.

The data at nodes SND1 and SND2 are transmitted to selecting gates 9607band 9607a through transfer gates SQB9 and SQB10 which are alreadyconductive in response to the signal DTS. Now, since word line SWL1 isselected and address signal Acdr is at "H", transistors SQB14 and SQB12are rendered conductive, and data on transfer gates 9606b and 9606a aretransmitted to SRAM bit line pair *SBL1 and SBL1. Consequently, data aretransferred to the corresponding SRAM memory cells. In FIG. 30, thereference character Ac represents the SRAM address in data transfer fromthe DRAM array to the SRAM array.

Then, after the data transfer from the DRAM array to the SRAM array, theDRAM is once returned to the standby state. When the DRAM array isrendered active, the data which has been latched in latch circuit 9603is transmitted to the DRAM array (global I/O lines GIO1 and *GIO1). Inthis case, data transfer designating signal DTA attains "H", transfergates 9604a and 9604b are rendered conductive, and data which has beenlatched in latch circuit 9603 is transmitted to global IO lines GIO1 and*GIO1. During data transfer from the latch circuit 9603 to the DRAMarray, the SRAM array can be independently accessed.

When the SRAM word line is selected, the SRAM bit line clamping signalSBLCL is set to "H" in order to surely set the amplifying transistorincluded in the amplifier circuit 9601 to conductive/non-conductivestate during data transfer. In this case, a structure may be used inwhich clamping function is set to non-operative state only during datatransfer, and the clamp signal SBLCL is always kept active when the SRAMarray is accessed with data transfer not being carried out. A structurefor block division or partial activation in which SRAM bit line pair isselected dependent on the even/odd row address may be used forwriting/reading of data of the SRAM array.

Data transfer operation between DRAM array and SRAM array will bediscussed in more detail later.

As described above, since one row of SRAM cells are divided into aplurality of groups and a plurality of word lines are arrangedcorresponding to respective groups for each row, an SRAM array which canhave an arbitrary shape without changing memory structure of rows andcolumns can be provided.

Since the shape of the SRAM array can be arbitrary selected, the degreeof freedom in designing the SRAM array arrangement is improved.Therefore, an SRAM array having optimal shape for the DRAM array can bearranged, and therefore a semiconductor memory device containing a cachehaving high density and high degree of integration effectively utilizingchip area can be provided.

Since the shape of the SRAM array can be changed without changing thememory structure, a semiconductor memory device which can be containedeasily in a package having an arbitrary shape can be provided.

[Pin Arrangement]

FIG. 31 shows an example of a pin arrangement of a package housing theCDRAM having the array arrangement [Array Arrangement 3] shown in FIG.10. As shown in FIG. 10, the CDRAM contained in the package of FIG. 31includes a 4M bit DRAM and a 16K bit SRAM integrated on one chip. TheCDRAM is housed in a 300 mil TSOP (Thin Small Outline Package) of typeII with lead pitch of 0.8 mm, chip length of 18.4 mm and 44 pins.

The CDRAM has two data input/output modes, that is, D/Q separation andmasked write. D/Q separation is a mode of inputting/outputting writedata D and output data Q through separate pins. Masked writing is anoperation mode in which write data D and read data Q are output throughthe same pin terminal, and writing of external data can be masked.

In order to effectively supply the supply voltage to CDRAM and tofacilitate layout of power supply interconnection, three pins areprovided for each of the supply potential Vcc and Gnd. Morespecifically, external supply potential Vcc is supplied to pins of thepin numbers 1, 11 and 33. The supply potential Vcc supplied to the pins1, 11 and 33 may have the same voltage values as the operational supplypotential Vcc. Alternatively, the external supply potential Vcc suppliedto the pins 1, 11 and 33 may be lowered in the device to supply theoperational supply potential. The ground potential GND is supplied tothe pins of the numbers 12, 22 and 34. Pins of the numbers 11, 12, 33and 34 at the center provide operational power supply for SRAM, whilepins of the numbers 1 and 22 provide power supply for DRAM.

A cache inhibiting signal CI# indicating cache access inhibition isapplied to a pin terminal of the number 4. When the cache inhibitionsignal CI# is set to "L", access to the SRAM array is inhibited, anddirect access (array access) to the DRAM array is allowed.

A write enable signal W# indicating data writing mode is applied to thepin of the number 5. A chip select signal E# indicating that this chipis selected, is applied to a pin of the number 18.

A command register designating signal CR# for designating the specialmode is applied to a pin of the pin number 23. When the command registerdesignating signal CR# is "L", command addresses Ar0 and Ar1 applied tothe pins of the numbers 2 and 3 are rendered valid, enabling setting ofthe special mode (selection of a register).

A cache hit signal CH# indicating a cache hit is applied to a pin of thepin number 27. If the cache hit signal CH# is "L", access to the cache(SRAM) is possible. An output enable signal G# indicating an output modeis applied to a pin of the number 40. A clock signal K is applied to thepin of the number 41.

A refresh designating signal REF# designating refreshing of the DRAMarray is applied to a pin of the number 44. When the refresh designatingsignal REF# attains to "L", automatic refreshing of the DRAM arrayinside is carried out in the cycle.

When self refreshing is designated, the pin terminal of the pin number44 is switched to an output terminal. When self refreshing is effected,a signal BUSY# indicating execution of self refreshing is output fromthe pin terminal of the pin number 44. It becomes possible to know thetiming of the self refreshing outside the CDRAM by this signal BUSY#,and therefore self refreshing can be utilized in a normal cycle.

Different data are applied to the pins of the numbers 9, 10, 13, 14, 31,32, 35 and 36 dependent on the two different operation modes, that is,D/Q separation and masked write. The operation modes of D/Q separationand masked write are set by a command register (which will be describedlater).

In masked write mode, pins of the numbers 10, 13, 32 and 35 are used ascommon data input and output terminals for commonly carrying out datainput/output. Pins of the numbers 9, 14, 31, 35 and 36 receive maskedwrite designating data M0, M1, M2 and M3 for indicating which dataapplied to which input/output pins should be masked, respectively.

In D/Q separation mode, pins of the numbers 9, 14, 31 and 36 are used aspins for inputting write data D0, D1, D2 and D3. Pins of the numbers 10,13, 32 and 35 are used as data output pins for outputting read data Q0,Q1, Q2 and Q3.

SRAM addresses Ac0 to Ac11 and DRAM addresses (array addresses) Aa0 toAa9 are applied through separate pin terminals and independent from eachother. In the pin arrangement shown in FIG. 31, external operationcontrol signals generally used in a standard DRAM, that is, row addressstrobe signal/RAS and column address strobe signal/CAS are not used. Inthe CDRAM contained in the package of FIG. 31 (see FIG. 10), data andcontrol signals are input in response to a rising edge of an externalclock signal K.

[Internal Function]

In this section, internal functions of CDRAM are briefly described.

(i) FIG. 32 is a block diagram showing internal structure of the CDRAMchip housed in a package of FIG. 31. The block arrangement shown in FIG.31 is for the purpose of functionally showing the internal structure ofthe CDRAM, and it should be noted that the structure shown in thisfigure is not the same as the actual layout.

Referring to FIG. 32, a CDRAM includes a DRAM 100 and a SRAM 200. DRAM100 comprises a 4M bit DRAM array 101; a DRAM row decoder block 102 fordecoding an applied internal row address for the DRAM and for selecting4 rows from DRAM array 101; a DRAM column decoder block 103 for decodingapplied internal column address for DRAM and for selecting one columnfrom each of the selected 4 rows in a normal operation mode (arrayaccess); and a block 104 including DRAM sense amplifiers DSA fordetecting and amplifying data of the memory cells connected to theselected rows, and selecting gates SG responsive to a column selectingsignal from block 103 for selecting 16 bits of DRAM array 101 in a datatransfer mode and for selecting 4 bits of memory cells in an arrayaccess mode.

SRAM 200 comprises an SRAM array 201 having the capacity of 16K bits; aSRAM row decoder block 202 for decoding an internal row address for theSRAM and for selecting 4 rows from SRAM array 201; and a columndecoder/sense amplifier block 203 including SRAM column decoders andSRAM sense amplifiers for decoding the internal column address for theSRAM, selecting 1 bit from each of the selected 4 rows and connect thesame to an internal data bus 251, and for detecting and amplifyinginformation of the selected SRAM cells in data reading. A bi-directionaltransfer gate circuit 210 is provided between DRAM 100 and SRAM 200.Referring to FIG. 32, the gate circuit 210 may be connected to an output(input) of the column decoder/sense amplifier block 203, as in thearrangement of FIG. 10. However, in FIG. 32, data input/output to andfrom DRAM 100 are carried out through the common data bus 251 in thearray access mode, and therefore the common data bus 251 is shown ascoupled to bi-directional transfer gate circuit 210.

The CDRAM in accordance with the present invention further comprises acontrol clock buffer 250 receiving externally applied control signalsG#, W#, E#, CH#, CI#,REF# and CR# to generate internal control signalsG, W, E, CH, CI, REF and CR; an address buffer 252 for generating aninternal address int-Aa for the DRAM and an internal address int-Ac forthe SRAM; and a clock buffer 254 for buffering an externally appliedclock signal K. Control clock buffer 250 takes an applied control signaland generates an internal control signal in response to a rise of aninternal clock from clock buffer 254. An output from clock buffer 254 isalso applied to address buffer 252. Address buffer 252 takes anexternally applied addresses Aa and Ac which are applied when theinternal chip enable signal E is active at a rising edge of the clock Kfrom the clock buffer 254 and generates internal addresses int-Aa andint-Ac.

The CDRAM includes a refresh circuit 290 for refreshing memory cells inDRAM array 100. Refresh circuit 290 includes a counter circuit 293 whichis activated in response to internal refresh designating signal REF forgenerating a refresh address of the DRAM array; and an address multiplexcircuit 258 for applying either a refresh address from counter circuit256 or an internal row address from address buffer 252 to DRAM rowdecoder block 102 in response to a switching signal MUX from a refreshcontrol circuit 292. Refresh control circuit 292 is driven in responseto a refresh request from an automatic refresh mode detecting circuit291. The refresh operation will be described later.

The CDRAM further comprises a DRAM array driving circuit 260 responsiveto the internal control signals E, CH, CI and REF for generating variouscontrol signals for driving DRAM 100; a transfer gate controllingcircuit 262 responsive to the internal control signals E, CH and CI forgenerating signals for controlling transfer operation of bi-directionaltransfer gate 210; and a SRAM array driving circuit 264 responsive tointernal chip select signal E for generating various control signals fordriving SRAM 200.

The CDRAM in accordance with the present invention further comprises acommand register 270 which is activated in response to an internalcontrol signal CR for generating a command CM for designating operationmode of the CDRAM in response to external write enable signal W# and tocommand addresses Ar (Ar0 and Ar1); a data input/output control circuit272 for controlling data input/output in accordance with the internalcontrol signals G, E, CH, CI and W and to the special mode command CM;an input/output circuit 274 formed of an input/output buffer and anoutput register for inputting/outputting data between common data bus251 and the outside of the device. An output register is provided in theinput/output circuit 274 for realizing a latched output mode and aregistered output mode, which are the special modes of the CDRAM. Datainput/output control circuit 272 sets input/output timing of data inaccordance with the mode designated by the special mode command CM aswell as the manner of input/output of data. In FIG. 32, manners of datainput/output pins in masked write mode is shown as an example.

The CDRAM further includes an additional function control circuit 299for realizing various functions. Functions realized by additionalfunction control circuit 299 will be described in detail later. Thefunction includes prohibition of generation of internal clocks at thetime of standby, switching between autorefresh/self refresh, switchingof address generating source in burst mode, and the like. Structures ofvarious circuits will be described in the following.

[Input/Output Circuit]

(Connection Between DRAM Array, SRAM Array and Internal Data Line)

FIG. 33 shows one example of manner of connection of bi-directionaltransfer gate circuit (BTG) and internal common data line 251 shown inFIG. 32. Referring to FIG. 33, a SRAM input/output gate 301 comprisesSRAM sense amplifier SSA and write circuit WRI which is activated indata writing to SRAM array for transmitting data on internal data line251a to a corresponding SRAM bit line pair SBL. SRAM bit line pair SBLis connected through SRAM sense amplifier SSA and SRAM column selectinggate 302 to internal data line 251a. A SRAM column selecting signal SYLfrom SRAM column decoder block 203 is applied to SRAM selecting gate302. Consequently, a pair of SRAM column bit line pair SBL only isconnected to internal data line 251a. Internal data line 251 shown inFIG. 32 transfers 4 bits of data, and only an internal data linecorresponding to 1 bit is shown in FIG. 33.

Referring to FIG. 33, the CDRAM further comprises an access switchingcircuit 310 responsive to a logical product signal on cache inhibitingsignal CI and DRAM column selecting signal DY for connecting global I/Oline pair GIO to internal data line 251a for enabling array access.Access switching circuit 310 and bi-directional transfer gate BTG areincluded in transfer gate circuit block 305.

The column selecting signal DYi of DRAM is generated by decoding, forexample, lower 4 bits of a column address. More specifically, 16 pairsof global I/O lines GIO are provided for one DRAM memory mat (having thecapacity of 1M bits). For array accessing, only one pair must beselected therefrom. Therefore, column selecting signal DYi is generatedby decoding lower 4 bits of column address for DRAM.

The access switching circuit 310 simply connects global I/O line pairGIO to internal data line 251a, and connection to corresponding signallines are carried out in bi-directional transfer gate BTG. A structurein which global I/O line pair GIO is connected to internal data line251a through SRAM sense amplifier SSA may be used to realize arrayaccessing, without providing such an access switching circuit 310. Atthis time, column selecting signal applied to SRAM selecting gate 302 isa selecting signal based on column address to the DRAM. This is realizedby a circuit multiplexing the column selecting signal by the signal CI.Such a multiplex circuit applies column selecting signal for DRAM toSRAM selecting gate, when the signal CI is active.

In the SRAM, a SRAM sense amplifier SSA is provided for each SRAM bitline pair SBL. However, one SRAM sense amplifier may be provided for theSRAM bit line pairs of 1 block, as in a normal SRAM. However, when theSRAM sense amplifier is provided for each SRAM bit line SBL, output ofdata can be more surely carried out at high speed. If the SRAM senseamplifier SSA has the same structure as the DRAM sense amplifier, it isnot necessary to provide writing circuit WRI.

[Data Input/Output Circuitry with Reference to FIGS. 34 to 36: SeparatedDQ and D/Q Common Structure]

FIG. 34 shows a structure for realizing D/Q separation in input/outputcircuit 274. Referring to FIG. 34, input/output circuit 274 comprises anoutput buffer 320 which is activated in response to an internal outputenable signal G for generating output data Q from data on internal dataline 251a; an input buffer 322 which is activated in response to aninternal write designating signal W for generating internal write datafrom external write data D and transmitting the same to internal dataline 251; and a switch circuit 324 responsive to a D/Q separationdesignating bit CMa from command register 270 (see FIG. 32) forshort-circuiting an output from output buffer 320 and an input of inputbuffer 322. D/Q separation designating bit CMa is included in a specialmode designating command CM generated from command register 270. If theswitch circuit 324 is rendered conductive, input/output of data arecarried out through the same pin. If the switch circuit 324 is off,input/output of data are carried out through separate pins. Structurerelated to data input/output of 1 bit only is shown in FIG. 34 as arepresentative.

FIG. 35 shows connection between data input/output circuit and otherportions. Referring to FIG. 35, output buffer circuit 320 receives datafrom selected memory cell data of DRAM array or SRAM sense amplifier totransmit the same to an external output pin Q. A first input buffercircuit 322a is connected to external pin terminal Q, and a second inputbuffer circuit 320b is connected to an external data input pin terminalD. Outputs of the first and second input buffer circuits 322a and 322bare transmitted through an OR circuit 322c to internal data buses DBW,*DBW (251a). Enabling/disabling of the first and second input buffercircuits 322a and 322b are carried out in response to designation bit CMfrom command register (see FIG. 32). If the command register designatesD/Q separation mode, the first input buffer circuit 322a is disabled,and input buffer circuit 322b is enabled. If the designation bit CMdesignates masked write mode common to D/Q, the first input buffercircuit 322a is enabled and the second input buffer circuit 322b isdisabled.

In the structure shown in FIG. 35, data from SRAM sense amplifier aretransmitted to output buffer circuit 320, since this figure shows a casein which data of selected memory cells of the DRAM array are transmittedto internal data bus through column lines (bit lines) of SRAM array andthrough sense amplifiers of the SRAM. More specifically, this figureshows an example of the structure of FIG. 33 without the gate 310, inwhich column selecting signals SYLi and SYLj applied to gate 302 arecommonly used as the DRAM column decoder outputs DYi and DYj. Thisstructure will be described later.

FIG. 36 shows a further structure of the input/output circuit. Referringto FIG. 36, a transistor 324a which is turned on in response to thedesignation bit CMa is provided between output buffer circuit 320 andinput buffer circuit 322. A transistor gate 324b which is turned on inresponse to a complementary designation bit/CMa is provided betweeninput buffer circuit 322 and a data input pin terminal D. In thisstructure, when designation bit CMa designates D/Q separation mode, thetransistor gate 324a is turned off, and the transistor gate 324b isturned on. Conversely, if the designation bit CMa designates maskedwrite mode with common D/Q pin, the transistor gate 324a is turned onand the transistor gate 324b is turned off.

By this structure, input buffer circuit 322 can be selectively connectedto data output pin terminal Q or to data input pin terminal D, wherebyD/Q separation mode and D/Q common mode can be selectively set.

[Data Output Modes of Transparent, Latched and Registered Modes withReference to FIGS. 37 through 43B]

A circuit structure for setting a data output mode of the input/outputcircuit will be described. The data output mode is set by a commandregister.

The data output mode is set to transparent mode, latch mode or registermode in accordance with the set data set in the command register.

FIG. 37 shows a circuit structure related to setting of data outputmode. Referring to FIG. 37, command register 270 includes a commandregister mode selector 279 responsive to a command register modedetecting signal (internal command register signal) CR for decodingwrite enable signal W# and command data Ar0 and Ar1, registers WR0-WR3,and a flipflop FF1. Command register includes 8 registers RR0-RR3 andWR0-WR3, as will be described later. However, in FIG. 37, registers RR2and RR3 are not shown. Each of the registers WR0-WR3 is a 4-bitregister. Registers RR0 and RR1 share one flipflop FF1. When registerRR0 is selected, flipflop FF1 is set to masked write mode. When registerRR1 is selected, flipflop FF1 is set to D/Q separation mode in which Dpins and Q pins are separated. An input control circuit 272b selectseither an input circuit 274b or 274c dependent on the data set in theflipflop FF1.

By decoding command data Ar0 and Ar1, it is determined to which registerWR0-WR3 the data is to be set. When write enable signal W# is active, 4bits of data D0-D3 (or DQ0-DQ3) are set to a corresponding register,through the input circuit 274b or 274c selected by input control circuit272b. Since register WR0 is related to data output mode, setting of dataoutput mode will be described. Output control circuit 272a is set in atransparent, latched or registered output mode in accordance with lower2 bits of data of the register WR0, and it outputs control signals φ1,/φ1 and φ2 for selectively activating output circuit 274a, dependent onthe set output mode.

FIG. 38 shows an example of a specific structure of the output circuit274a. Referring to FIG. 38, output circuit 274a includes a first outputlatch 981 responsive to control signals φ1 and /φ1 for latching data onread data buses DB and *DB, a second output latch 982 responsive to aclock signal φ2 for passing data latched in output latch 1 or data ondata buses DB and *DB, and an output buffer 983 receiving data fromoutput latch 982 for transmitting the same as output data to an externalpin terminal DQ in response to control signal G#.

First output latch 981 includes clocked inverters ICV1 and ICV2 whichare activated in response to clock signals φ1 and /φ1. An input and anoutput of clocked inverter ICV1 are connected to an output and an inputof clocked inverter ICV2, respectively. Output latch 981 is set to alatched state when clock signal φ1 is "H". Namely, clocked invertersICV1 and ICV2 are activated when clock signal φ1 is "H" and serve as aninverter. When clock signal φ1 is "L", clocked inverters ICV1 and ICV2are disabled, and latch 981 does not carry out latching operation.

Second output latch 982 latches data applied to inputs A and *A andoutputs the data from outputs Q and *Q, when clock signal φ2 is at "L".Output latch 982 outputs data latched when clock signal φ2 is at "L"from outputs Q and *Q regardless of the signal state at inputs A and *A,when clock signal φ2 is "H". Clock signals φ1, /φ1 and φ2 controllingthe latching operation are synchronous with external clock K, andtimings of generation thereof are made different from each other byoutput control circuit 272a.

Output buffer 983 is activated when output enable signal G# is madeactive, and transmits output data from output latch 982 to a terminalDQ.

FIG. 39 shows an example of a specific structure of second output latch982. Referring to FIG. 39, second output latch 982 includes a D flipflopDFF receiving an input A (*A) at a D input thereof and receiving clocksignal φ2 at its clock input CLK. An output Q (*Q) of output latch 982is provided from output Q of the flipflop DFF. The D flipflop DFF is ofa down edge trigger type. It takes an input A at a timing of a fall ofthe clock signal φ2 to L, and outputs input A as received while clocksignal 42 is "L". When clock signal φ2 is at "H", it outputs previouslylatched data, regardless of the state of the input A applied to inputterminal D. Thus, an output latch 982 realizing desired function isprovided. D type flipflop DFF is provided for each of the inputs A and*A. The output latch 982 may have other structure. Any circuit structurecapable of realizing latched state and through state in response toclock signal φ2 may be used.

FIG. 40 shows an example of a specific structure of the output controlcircuit 271a. Output control circuit 272a includes delay circuits 981a,981b and 981c for providing a predetermined time delay to the externalclock; a one shot pulse generating circuit 992a for generating a oneshot pulse signal having a predetermined pulse width in response to anoutput from delay circuit 991a; a one shot pulse generating circuit 992bfor generating a one shot pulse signal having a predetermined pulsewidth in response to an output from delay circuit 991b; and a one shotpulse generating circuit 992c for generating a one shot pulse signalhaving a predetermined pulse width in response to an output from delaycircuit 991c. Clock signals φ1 and /φ1 are generated from one shot pulsegenerating circuit 992a.

Outputs from one shot pulse generating circuits 992b and 992c areapplied to an OR circuit 993. Clock signal φ2 is generated from ORcircuit 993. Delay time provided by the delay circuit 991b is shorterthan the delay time provided by the delay circuit 991c. Enable/disableof one shot pulse generating circuits 992a to 992c is set by 2 bits ofcommand data WR0. When 2 bits of command data WR0 represents latch mode,one shot pulse generating circuits 992a and 992c are enabled, and oneshot pulse generating circuit 992b is disabled. Operation of the commandregister and the data output circuit shown in FIGS. 37 to 40 will bedescribed.

First, latch operation will be described with reference to FIG. 41,which is a diagram of signal waveforms. Latched output mode as the dataoutput mode is set by setting lower 2 bits of command data register WR0to (01). At this time, one shot pulse generating circuits 992a and 992care enabled. Let us assume that output enable signal G# is at an activestate of "L", indicating data output. At this time, an external addressAn is taken into an address buffer at a rising edge of the clock K, acorresponding SRAM word line SWLn is selected, and data RDn appears onthe SRAM bit line SBL. At this time, one shot pulse generating circuit992a generates a one shot pulse at a predetermined timing in response tothe rise of external clock K, and is kept at "L" for a predeterminedtime period. When the clock signal φ1 falls to "L", latch operation ofoutput latch 981 is prohibited. At this time, clock signal φ2 is at "H"maintaining the latch state, latches and outputs data Qn-1 which hasbeen read in the previous cycle. 4 bits of data selected in accordancewith an external address out of 64 bits of data RDn on the SRAM bit linepair SBL which has been selected by the external address are transmittedto internal output data buses DB and *DB. With the data DBn on databuses DB and *DB being established, the clock signal φ1 rises to "H".Consequently, output latch 981 carries out latching operation to latchthe established data DBn.

Thereafter, a one shot pulse is generated from one shot pulse generatingcircuit 992c and signal φ2 falls to "L". Consequently, output latch 982newly takes the latched data DBn and transmits the same to outputterminal DQ through an output buffer 983. The clock signal φ2 isgenerated in synchronization with a fall of the clock K, and in responseto a fall of the external clock K, data DBn selected in this cycle isoutput as output data Qn. Clock signal φ2 rises to "H" by the time theexternal clock K rises again. Consequently, output latch 982continuously output established data DBn regardless of the data oninternal output data buses DB and *DB.

Thereafter, clock signal φ1 is set to "L" and latch state of outputlatch 981 is released, so as to be ready for the next cycle, that is,latching operation of the next established data. Consequently, inresponse to a rise of the external clock K, data read in the previouscycle are output successively as established data.

Register mode will be described with reference to FIG. 42. Setting ofthe register mode is done by setting lower 2 bits of command data WR0 to(11). In registered output mode, one shot pulse generating circuit 992bis enabled, and one shot pulse generating circuit 992c is disabled. Atthis time, in response to a rise of the external clock K, a one shotpulse which falls to "L" is generated from one shot pulse generatingcircuit 992b. Since clock signal φ1 is at "H" at this time, data DBn-1which has been read in the previous cycle is latched by output latch982.

In registered output mode, timing of falling of clock signal φ2 to "L"is determined in response to a rise of external clock K. In this case,in response to (n+1) th cycle of the external clock K, data DBn read innth clock cycle is output as output data Qn at output pin terminal DQ.Namely, only the timing of generation of the clock signal φ2, that is,timing of falling thereof to "L" is different between latched outputmode and registered output mode. Consequently, latched output mode inwhich data of previous cycle is output and data read in the presentcycle is output continuously, and registered output mode in which dataread in nth cycle is output at (n+1) th cycle are realized.

Transparent mode will be described with reference to FIGS. 43A and 43B.A first transparent output mode will be described with reference to FIG.43. As described above, transparent output mode is realized by settinglower 2 bits of the register WR0 to (X0). The first transparent outputmode or a second transparent output mode is selected by setting the bitvalue of X to 0 or 1. Either first transparent output mode or secondtransparent output mode may be selected arbitrarily corresponding toeither of the values of X. In first transparent output mode, clocksignals φ1 and φ2 are both maintained at "L". At this time, latchoperation in output latch 981 is released, and output latch 982 is in athrough state. Therefore, in this case, data DBn transmitted to internaldata buses DB, *DB are directly output as output data Qn. If data on theSRAM bit line pair SBL or global I/O line pair GIO is invalid data(INVALID DATA), invalid data INV appears on output pin DQ in response.

In second transparent output mode shown in FIG. 43, clock signal φ1 isgenerated. First output latch 981 carries out latching operation whileclock signal φ1 is at "H". Therefore, even if data RDn on SRAM bit linepair SBL is set to an invalid state, data on data buses DB and *DB arelatched as valid data by latch circuit 891 and output for apredetermined time period (while the clock signal φ1 is at "H").Therefore, a period in which invalid data INV is output can be madeshorter. In second transparent output mode, clock signal φ2 is also keptat "L".

Although a D flipflop of a down edge trigger type has been used assecond output latch 982 in the above described structure, an up edgetrigger type latch circuit may be used to provide the same effect, bychanging polarity of the clock signal φ2. The structure of output latch981 can also be implemented by other latch circuits.

The characteristics of the output modes set by the common register areas follows.

(1) Transparent output mode: In this mode, data on internal data busesDB, *DB are directly transmitted to an output buffer. In this mode,valid data as output data DQ (Q) appears after a time lapse of tKHA(array access time) from a rising edge of external clock K or after alapse of a time period tGLA (access time from the signal G# has reached"L" to an output of a valid data) from a falling edge of output enablesignal G#, which is later. If output enable signal G# falls before thetime tKHA, invalid data (INV) is kept continuously output to tKHA, sincevalid data has not yet appeared on internal data buses DB and *DB, ifoutput enable signal G# falls at an earlier timing. Therefore, in thismode, a period in which output data is valid is limited to a period inwhich valid data is appearing on the internal bus.

(2) Latched output mode: In this mode, an output latch circuit isprovided between the internal data buses DB and *DB and the outputbuffer. In the latched output mode, data is latched by an output latchcircuit while external clock K is at "H". Therefore, when output enablesignal G# falls before the time tKHA, data read in the previous cycle isoutput. Therefore, even if invalid data has appeared on internal databuses DB and *DB, invalid data is not output externally. Namely, thismode provides an advantage that sufficient time period for the CPU totake output data in can be provided.

(3) Registered output mode: In this mode, an output register is providedbetween the internal data bus and the output buffer. In the registeredoutput mode, valid data of the previous cycle is output as output dataafter a lapse of tKHAR from a rising edge of external clock K or after alapse of tGLA from a falling edge of output enable signal G#, which islater. From the same reason as in the latch mode, invalid data is notoutput in register mode. When data are to be output continuously inregister mode, it seems that data are output at very high speed in viewof the rise of the external clock K. Such operation is generally calleda pipeline operation, in which an apparent access time can be furtherreduced from the cycle time.

Since the above described output modes can be set by command registers,a user can select an output mode suitable for a system.

[Data Transfer Between DRAM and SRAM]

Now, the data transfer between DRAM array and SRAM will be described indetail with reference to FIGS. 44 through 60D. Transfer mode includes(a) block transfer mode from DRAM to SRAM, (b) copy back mode from SRAMto DRAM and (c) fast copy back mode with block transfer and copy backmodes in parallel. In the following description, no multiple word linescheme in SRAM array is assumed. However, the data transfer method inthe following is also applicable to multiple SRAM word line structure.

FIG. 44 shows one example of a structure of bi-directional transfer gateBTG. Referring to FIG. 44, bi-directional transfer gate BTG (BTGa orBTGb) comprises a drive circuit DR1 which is activated in response todata transfer designating signal φTSD for transmitting data on SRAM bitline pair SBL to global I/O line pair GIO, and a drive circuit DR2 whichis activated in response to data transfer designating signal φTDS fortransmitting data on global I/O line pair GIO to SRAM bit line pair SBL.Drive circuits DR1 and DR2 are set to an output high impedance statewhen data transfer designating signals φTSD and φTDS are inactive.

(a) FIG. 45 is a diagram of signal waveforms showing operation when dataare transferred from DRAM array to SRAM array. Data transfer operationfrom DRAM array to SRAM array will be described with reference to FIGS.78 and 44.

While precharge designating signal φEQ is at an active state "H" beforetime t1, sense amplifier driving signal lines φSAN, /φSAP, local I/Oline pair LIO and global I/O line pair GIO are maintained at a prechargepotential of Vcc/2. At this time, precharge equalize circuit PE isactivated to precharge DRAM bit line pair DBL to the precharge potentialof Vcc/2 (=Vb1) and equalizes potentials of the bit lines BL, /BL.

When precharge designating signal φEQ falls at t1, precharge equalizecircuit PE and equalize transistor TEQ are rendered inactive.Consequently, equalizing operation of the sense amplifier driving signallines φSAN and /φSAP is completed, equalize/precharge operation of DRAMbit line pair DBL is stopped, and DRAM bit line pair DBL and senseamplifier driving signal lines φSAN and /φSAP are set to a floatingstate at the intermediate potential Vcc/2 (where Vss=0 V).

Thereafter, in accordance with an externally applied address, rowselecting operation is effected by row decoder 14 (see FIG. 7), one wordline DWL is selected in DRAM array 1 (see FIG. 7) at t2, and potentialof the selected word line DWL rises to "H". One row of memory cellsconnected to the selected word line DWL are connected to correspondingDRAM bit line pair DBL (DRAM bit line BL or /BL), and potential ofrespective DRAM bit lines changes dependent on data of the memory cellconnected thereto. FIG. 45 shows potential change of a DRAM bit linepair DBL when a memory cell storing the potential "H" is selected.

At time t3, sense amplifier activating signal φSANE rises from groundpotential Vss to the operational supply potential Vcc level, andtransistor TR2 in sense amplifier activating circuit SAK is turned on.Consequently, the second sense amplifier portion in DRAM sense amplifierDSA is activated, and a bit line of lower potential in the DRAM bit linepair DBL is discharged to the level of the ground potential GND.

At time t4, sense amplifier activating signal /φSAPE falls from thepotential Vcc to the ground potential GND level, and transistor TR1 insense amplifier activating circuit SAK is turned on. Consequently, thefirst sense amplifier portion of DRAM sense amplifier DSA is activated,and the bit line of higher potential in the DRAM bit line pair DBL ischarged to the level of the operational supply potential Vcc.

At time t5, in accordance with a column selecting signal from DRAMcolumn decoder 15 (see FIG. 7), one column selecting line CSL isselected, and potential of the selected column selecting line CSL risesto "H". Consequently, two pairs of DRAM bit line pairs DBL are connectedto local I/O line pairs (LIOa and LIOb) through the column selectinggate CSG. Consequently, potential on the selected DRAM bit line pair DBLis transmitted to local I/O line pair LIO, and potential of local I/Oline pair changes from the precharge potential Vcc/2.

At time t6, block activating signal φBA rises to "H" only for theselected row block, and I/O gate IOG is turned on. Consequently, signalpotential on local I/O line pair LIO is transmitted to global I/O linepair GIO. "Selected row block" means a row block including the selectedword line DWL. Designation of the selected row block is effected bydecoding, for example, upper 2 bits of the row address used forselecting the DRAM word line. By such block dividing operation, currentconsumption can be reduced.

In SRAM, row selecting operation is done by SRAM row decoder 21 (seeFIG. 7) at time ts1, one SRAM word line SWL is selected in SRAM array,and potential of the selected SRAM word line SWL rises to "H". Rowselecting operation in DRAM and row selecting operation in SRAM arecarried out in an asynchronous manner. Data of SRAM cells connected tothe SRAM word line SWL are transmitted to corresponding SRAM bit linepair SBL. Consequently, potential of SRAM bit line pair SBL changes fromthe precharge potential Vcc/2 to potential corresponding to theinformation stored in the corresponding SRAM cell.

At time t7, data transfer designating signal φTDS attains to and ismaintained at "H" for a predetermined time period. Before t7, data ofDRAM cell has been already transmitted to the global I/O line pair GIO,and SRAM cells have been connected to SRAM bit line pair SBL. Inresponse to data transfer designating signal φTDS, bi-directionaltransfer gate BTG is activated and it transmits signal potential onglobal I/O line pair GIO to the corresponding SRAM bit line pair SBL.Consequently, data are transmitted from DRAM cells to SRAM cells.

Time relation between ts1, t1 and t6 is arbitrary, provided that thetime t7 at which data transfer designating signal φTDS is activated isafter t6 at which block activating signal φBA rises and after ts1 atwhich SRAM word line SWL is selected. In this cycle, data transferdesignating signal φTSD designating transfer from SRAM to DRAM is keptat inactive state, that is, "L".

At time t8, potential of the selected DRAM word line DWL falls to "L",at time ts2, potential of the selected SRAM word line SWL falls to "L",and various signals are returned to the initial state. Thus, the datatransfer cycle from DRAM to SRAM is completed.

As described above, DRAM column decoder 15 (see FIG. 7) selects onecolumn selecting line CSL in each column block 12. One column selectingline CSL selects two pairs of DRAM bit lines DBL. Data transfer fromDRAM to SRAM is carried out column block by column block in parallel.Therefore, in the embodiment shown in the figure, 16 bits of data aretransferred simultaneously. This relation is realized in a structurehaving 8 column blocks and in which two pairs of DRAM bit lines areselected in each column block. The number of bits of the datatransferred at one time changes dependent on the number of DRAM bit linepairs selected at one time or dependent on the number of column blocks.Therefore, appropriate block size can be set.

(a) Another Transfer Timing from DRAM to SRAM

As shown in FIG. 45, when DRAM word line driving signal DWL falls to "L"of the inactive state approximately at the time t8, data transferdesignating signal φTDS falls to "L" in response. At this time t8, localI/O line pair LIO is disconnected from SRAM bit line pair SBL, and DRAMarray and SRAM are electrically separated. After the time t8, DRAMportion and SRAM portion can operate independent from each other.Therefore, as shown in FIG. 46, when data transfer designating signalφTDS is made inactive at time t8', the word line driving signal DWL inDRAM array is still maintained at the active state, that is, "H". Atthis time, the DRAM cannot be newly accessed externally, but SRAM arrayportion can be externally accessed.

More specifically, as shown in FIG. 46, when data transfer designatingsignal φTDS falls to "L" at time t8' and even if DRAM array is active atthat time, SRAM array can be newly accessed after the lapse of apredetermined time period from time ts2 at which it is set to thestandby state. Therefore, after the time t8', SRAM portion can beaccessed regardless of the state of DRAM. For example, at time t8', dataat a cache miss can be read from SRAM array.

Further, before the DRAM is returned to the standby state, SRAM can beaccessed by newly setting an external address. The reason for this isthat RAS precharging operation necessary for a DRAM is not necessary forthe SRAM and the SRAM can be accessed at high speed after the return tothe standby state.

Referring to FIG. 46, DRAM word line driving signal DWL falls to "L" attime t9'. When equalize signal φEQ is activated at time t10, equalizeand precharge operations of DRAM bit line pair DBL is started. At thistime, equalizing operation of sense amplifier driving signal lines φSANand /φSAP is also carried out. DRAM together with peripheral circuitsthereof are returned to the standby state at a time t11 after severaltens nsec from time t9'. The DRAM array cannot be accessed until apredetermined RAS precharge time period has lapsed. However, in SRAMarray, at time ts3 after several nsec from time ts2 at which the SRAMword line SWL1 is set to the non-selected state, it is possible toselect a different SRAM word line SWL2 in accordance with an externaladdress and to access (read data from or write data to) memory cellsconnected to the selected SRAM word line SWL2.

Time interval between ts2 at which data transfer designating signal φTDSfalls to the inactive state "L" and ts3 at which SRAM word line SWL2 canbe activated is set at an appropriate value by external specification.Since access to the SRAM is made possible before DRAM is returned to thestandby state, a semiconductor memory device especially a semiconductormemory device containing a cache which operates at high speed, can beprovided.

Since it is not necessary in SRAM to carry out column selectingoperation after the sensing and latch operation of the sense amplifieras in the DRAM, a very short time period is enough for the selectingperiod of the word line SWL2 in SRAM. At time ts4, access to the SRAM iscompleted. In a normal SRAM, the time period from ts3 to ts4 is about 10nsec at the most. Access to the SRAM is completed during the standbystate of the DRAM. The structure enabling access to the SRAM before theDRAM array is returned to the standby state is realized by thesemiconductor memory device of the present invention in which SRAM andDRAM can be accessed by designating addresses, which addresses areindependent from each other.

(b) Data Transfer from SRAM to DRAM

FIG. 47 is a diagram of signal waveforms showing operations in datatransfer from SRAM to DRAM. The data transfer operation from SRAM toDRAM will be described with reference to FIGS. 7, 8 and 47. Theoperation in the DRAM portion from t1 to t6 is the same as that in datatransfer from the DRAM to SRAM shown in FIG. 45. As to the operation ofthe SRAM portion, potential of SRAM word line SWL rises to "H" at timets1, as in the signal waveform of FIG. 45.

After the time ts1 and t6, that is, after DRAM bit line pair DBL isconnected to global I/O line pair GIO and SRAM cells (SMCs) areconnected to SRAM bit line pair SBL, data transfer designating signalφTSD is activated and rises to "H" for a predetermined time period aftert7. In response, bi-directional transfer gate BTG is activated andtransmits signals on SRAM bit line pair SBL to DRAM bit line pair DBLthrough global I/O line pair GIO (GIOa, GIOb) and through local I/O linepair LIO (LIOa, LiOb). Consequently, data of the DRAM cells connected tothe selected DRAM bit line pair DBL are rewritten. Namely, data in theSRAM cells are transferred to the DRAM cells. In the data transfer cyclefrom SRAM array to DRAM array, data transfer designating signal φTDS ismaintained at inactive state, that is, "L".

The data transfer operation shown in FIGS. 45 to 47 is effected when acache miss occurs with the SRAM array used as a cache. Morespecifically, when data to which access is requested by a CPU, which isan external processing unit, is not stored in the SRAM array, necessarydata is transferred from DRAM array to SRAM array. At a cache miss, acopy back operation for transferring data from SRAM array to DRAM arrayas well as block transfer for transferring desired data from DRAM arrayto SRAM array are carried out. Copy back operation and block transferoperation will be described in the following.

Referring to FIG. 48A, let us assume that data D2 to which access isrequested by the CPU is not stored at a corresponding position of theSRAM. Data D1' is stored at the corresponding position of the SRAM, thatis, the cache. When the cache miss of the SRAM occurs, the DRAM is stillat a precharge state.

Referring to FIG. 48B, in response to a cache miss designating signal, aword line (shown by hatched portion) including the region to which dataD1' is to be stored is selected in the DRAM. This is an array activestate. In the SRAM, the region of the data D1' has been selected.

Referring to FIG. 48C, transfer designating signal φTSD is generated,and data D1' of the SRAM is transmitted to the corresponding region ofthe selected word line of the DRAM. Consequently, data D1' is stored inthe data region D1 of the DRAM.

Referring to FIG. 48D, after the completion of transfer of data D' tothe data region D1 of the DRAM, the DRAM array is returned to theprecharge state.

Referring to FIG. 48E, a word line (shown by a hatching) including dataD2 to which access is requested by CPU is selected in the DRAM.

Referring to FIG. 48F, data D2 included in the selected word line istransmitted to the corresponding region of the SRAM array in response todata transfer designating signal φTDS. Consequently, data D1 of the SRAMarray is rewritten by data D2. The copy back operation corresponds tothe FIGS. 48A to 48D, and the block transfer mode corresponds to FIG.48D to FIG. 48F. The step shown in FIG. 48D is included in both cycles,since the precharge period of the DRAM is considered to be included inboth cycles, when these two operations are carried out successively.

(c) Fast Copy Back Mode Operation

In this above method of data transfer, a precharging period of the DRAMarray is interposed, and direction of data transfer is always one way.Therefore, data transfer between SRAM array and DRAM array can not becarried out at high speed. Data transfer operation carried out at ahigher speed by overlapping data transfer to and from DRAM array andSRAM array will be described in the following.

FIG. 49 is a block diagram schematically showing another structure of adata transfer device. A circuit portion for transferring data of 1 bitbetween SRAM array and DRAM array in the data transfer device is shownin FIG. 49. The data transfer device includes 16×4 of the bi-directionaltransfer gate circuits shown in FIG. 49. In the following, the datatransfer device shown in FIG. 49 is referred to as a bi-directionaltransfer gate circuit for transferring data of 1 bit.

Referring to FIG. 49, the bi-directional transfer gate circuit includesa gate circuit 1810 responsive to transfer control signal φTSL forconnecting SRAM bit line pair SBLa and *SBLa to a latch circuit 1811; agate circuit 1812 responsive to transfer control signal φTLD fortransmitting data latched in latch circuit 1811 to global I/O lines GIOaand *GIOa; and a gate circuit 1813 responsive to DRAM write enablesignal AWDE and to SRAM column decoder output SAY for transferring dataon write data bus lines DBW and *DBW to global I/O lines GIOa and *GIOa.An output SAY of SRAM column decoder selects 1 bit out of 16 bits whichhas been simultaneously selected in DRAM array block. Therefore, astructure in which lower 4 bits of a column address signal for DRAMarray are applied to SRAM column decoder is shown as an example.

The bi-directional transfer gate circuit further includes an amplifiercircuit 1814 which is activated in response to transfer control signalφTDS for activating data on global I/O lines GIOa and *GIOa; and a gatecircuit 1815 responsive to transfer control signal φTDS for transferringdata amplified by the amplifier circuit 1814 to SRAM bit line pair SBLaand *SBLa.

Gate circuit 1810 and latch circuit 1811 constitute first transfermeans, gate circuit 1815 and amplifier circuit 1814 constitute secondtransfer means, and gate circuit 1812 and gate circuit 1813 constitute athird transfer means.

SRAM write enable signal AWDE is generated upon occurrence of a cachemiss in an array access cycle when CPU requests data writing. Morespecifically, it is generated from a transfer gate control circuit 262,which will be described later, when a chip select signal E# attains "L",cache hit signal CH# is "H" and write enable signal W# is "L" at arising edge of a clock signal K.

When data is to be written to DRAM array by gate circuit 1813, writedata can be directly transmitted to global I/O lines GIOa and *GIOa, notthrough SRAM bit line pair SBLa and *SBLa. Consequently, data can bewritten at a higher speed. Gate circuit 1812 is used for adjustingtiming, when 64 bits (in the case of 4 MCDRAM) of data are to besimultaneously transferred from SRAM array to DRAM array in response totransfer control signal φTLD. Similarly, gate circuit 1815 is used foradjusting timing when 64 bits of data are to be simultaneouslytransferred from DRAM array to SRAM array.

FIG. 50 shows an example of a specific structure of the bi-directionaltransfer gate circuit shown in FIG. 49.

Gate circuit 1810 includes n channel MOS transistors T102 and T103 foramplifying signal potential on SRAM bit line pair SBLa and *SBLa, and nchannel MOS transistors T100 and T101 which are rendered conductive inresponse to transfer control signal φTSL for transmitting data amplifiedby transistors T102 and T103 to a latch circuit 1811. Transistor T102has its gate connected to SRAM bit line SBLa, one conduction terminalconnected to the ground potential Vss and the other conduction terminalconnected to one conduction terminal of transistor T100. Transistor T103has its gate connected to SRAM bit line *SBLa, one conduction terminalconnected to the ground potential Vss and the other conduction terminalconnected to one conduction terminal of transistor T101.

Latch circuit 1811 includes inverter circuits HA10 and HA11 having theirinputs connected to the outputs of each other. Inverter circuits HA10and HA11 constitute an inverter latch. Latch circuit 1811 furtherincludes inverter circuits HA12 and HA13 for inverting latched data ofthe inverter latch (inverter circuits HA10 and HA11).

Gate circuit 1812 includes a gate circuit 1812b for transmitting data toglobal I/O line GIOa, and a gate circuit 1812a for transmitting data toglobal I/O line *GIOa. Gate circuit 1812a is formed by an n channel MOStransistor T105 and gate circuit 1812b is formed by an n channel MOStransistor T106. Transfer control signal φTLD is applied to the gates ofthe transistors T105 and T106.

Amplifier circuit 1816 includes an n channel MOS transistor T113 foramplifying potential on global I/O line *GIOa, an n channel MOStransistor T112 which is turned on in response to transfer controlsignal φTDS for transmitting data amplified by transistor T113 to nodeN100, a p channel MOS transistor T111 responsive to transfer controlsignal TDS for precharging node N110 to a supply potential Vcc, and a pchannel MOS transistor T110 which is connected in parallel to transistorT211 between power supply Vcc and a node N100.

Amplifier circuit 1814 further includes an n channel MOS transistor T117for amplifying signal potential on global I/O line GIOa, an n channelMOS transistor T116 which is turned on in response to transfer controlsignal φTDS for transmitting signal potential on global I/O line GIOaamplified by transistor T117 to node N110, a p channel MOS transistorT114 responsive to transfer control signal φTDS for precharging nodeN110 to supply potential Vcc, and a p channel MOS transistor T115 whichis connected in parallel to transistor T214 between power supply Vcc andnode N110.

Transistor T110 has its gate connected to node N110, and transistor T115has its gate connected to node N100. Transistors T110 and T115constitute a differential amplifying circuit.

Gate circuit 1815 includes a gate circuit 1815a for transferring data toSRAM bit line SBLa, and a gate circuit 1815b for transferring data toSRAM bit line *SBLa. Gate circuit 1815a includes an n channel MOStransistor T120 which is turned on in response to transfer controlsignal φTDS for transmitting signal potential on node N100 to SRAM bitline SBLa. Gate circuit 1815b includes an n channel MOS transistor T111which is turned on in response to a transfer control signal φTDS fortransmitting signal potential on node N110 to SRAM bit line *SBLa.

Gate circuit 1813 includes a gate circuit 1813a for transmitting signalpotential on internal data bus line *DBW to global I/O line *GIOa and agate circuit 1813b for transmitting signal potential on internal databus line DBW to global I/O line GIOa. Gate circuit 1813a includes an nchannel MOS transistor T130 which is turned on in response to an outputSAY from SRAM column decoder, and an n channel MOS transistor T131 whichis turned on in response to DRAM write enable signal AWDE. TransistorsT131 and T130 are connected in series between internal write data busline *DBW and global I/O line *GIOa.

Gate circuit 1813b includes an n channel MOS transistor T132 which isturned on in response to output SAY of SRAM column decoder, and an nchannel MOS transistor T133 which is turned on in response to SRAM writeenable signal AWDE. Transistors T132 and T133 are connected in seriesbetween internal data bus line DBW and global I/O line GIOa. Theoperation of the bi-directional transfer gate circuit will be describedin the following.

Referring to FIG. 51, data transfer operation in a cache miss writingoperation will be described. In a cache miss writing, chip select signalE# and write enable signal W# both attain to "L" and cache hit signalCH# attains to "H" at a rising edge of clock signal K (as will bedescribed in detail later). In response, DRAM and SRAM are bothactivated. An address applied to SRAM and DRAM at this time is appliedfrom CPU.

At time t1, precharge cycle is completed in DRAM, and a memory cycle isstarted. In response, equalize signal φEQ rises to an inactive state"L". By the time a DRAM word line DWL is set to a selected state inDRAM, signal potential on internal data bus line DBW has beenestablished to a value corresponding to write data. When a DRAM wordline DWL is selected and signal potential on DRAM bit line pair DBL ischanged at time t2, sense amplifier activating signals φSAN and /φSAPare activated at times t3 and t4, and signal potential on each DRAM bitline pair attains to a value corresponding to the read memory cell data.

In SRAM, a SRAM word line SWL is selected at time ts1. Data of memorycells connected to the selected word line SWL are transmitted to acorresponding SRAM bit line SBLa (*SBLa). When signal potential on SRAMbit line SBLa (*SBLa) is established, transfer control signal φTSL risesto "H", gate circuit 1810 is opened, and signal potential on SRAM bitlines SBLa and *SBLa are transmitted to latch circuit 1811. Morespecifically, in the circuit structure shown in FIG. 50, transistorsT100 and T101 are turned on, one of transistors T102 and T103 is turnedon and the other thereof is turned off, and the potential "L" istransmitted through the transistor (T102 or T103) which is on to latchcircuit 1811. Latch circuit 1811 latches the applied signal potential"L" at a corresponding node.

In DRAM, in parallel to the data latch operation of the latch circuit1811, column selecting line CSL is selected (time t5), and in response,potential on local I/O line pair LIO is established. Then, by the blockselecting signal φBA, potential on local I/O line pair LIO istransmitted to global I/O line pair GIO (t6).

When signal potential on global I/O line pair GIO is established, DRAMwrite enable signal AWDE rises to "H". At this time, output signal SAYfrom SRAM column decoder is set to an active state, and gate circuit1813 provided for one global I/O line out of 16 bits is opened.Consequently, write data appeared on data bus lines DBW and *DBW aretransmitted to global I/O lines GIOa and *GIOa through gate circuits1813b and 1813a.

When signal potential on global I/O line pair GIO has reached a valuecorresponding to write data at time t7, transfer control signal φTDSrises to "H" at time t7'. In response, transistors T111 and T114 areturned off, precharging of nodes N100 and N110 is stopped, andtransistors T110 and T115 differentially amplify signal potential onglobal I/O lines GIOa and *GIOa which have been transmitted throughtransistors T112 and T116. Consequently, signal potential on nodes N100and N110 attains to the potential which is the inversion of the signalpotential on global I/O lines *GIOa and GIOa.

For example, let us assume that signal potential on global I/O line GIOais "H" and that the signal potential on global I/O line *GIOa is "L". Atthis time, transistor T117 is turned on, and transistor T113 is turnedoff, potential at node N110 attains to "L" and potential at node N100attains to "H". The potential "L" at node N110 turns transistor T110 on,and potential "H" at node N100 turns transistor T115 off. By thetransistors T110 and T115, signal potentials on nodes N100 and N110 aredifferentially amplified and latched.

In parallel to the amplifying operation in amplifying circuit 1814, gatecircuits 1815a and 1815b are rendered conductive in response to a riseto "H" of transfer control signal φTDS, signal potential on node N100 istransmitted to GRAM bit line SBLa, and signal potential on node N110 istransmitted to SRAM bit line *SBLa. At this time, since transfer controlsignal φTLD is fixed at "L", gate circuits 1812a and 1812b are closed,and data latched in latch circuit 1811 is not transmitted to global I/Olines GIOa and *GIOa.

In DRAM array, write data transmitted to global I/O line pair GIO istransmitted to DRAM bit line pair DBL through local I/O line pair LIO.

At time t8, memory cycle of DRAM is completed, and precharge period isstarted. At time t9, a standby state for waiting the next cycle isstarted.

In SRAM, potential on SRAM word line SWL falls to "L" at time ts2, andthus one cycle is finished.

As described above, in a cache miss writing operation, by writing writedata to a corresponding memory cell of the DRAM array and bytransmitting the data changed by the external write data to the SRAMarray, writing of data to the memory cell in SRAM is completed when onedata transfer cycle is completed, and therefore even at a cache miss,data can be written at a high speed.

The above described data transfer operation (hereinafter referred to asa high speed copy back mode) is schematically shown in FIGS. 52A through52D. Data transfer operation in high speed copy back mode at a cachemiss writing operation will be described with reference to FIGS. 52Athrough 52D.

Let us assume that CPU generates a request for rewriting data D2 by D.At this time, at that region of the SRAM to which access is requested bythe CPU, data D1' has been stored, and data D2 is stored in DRAM array(FIG. 52A).

When such a cache miss writing occurs, first, in SRAM, data D1' istransferred to a latch (latch circuit 1811). In parallel to thistransferring operation, in DRAM, a word line (hatched portion) includingdata D2 is selected in accordance with an access from CPU, and writedata D is transmitted to the region storing data D2 connected to theselected word line (FIG. 52B). Consequently, data D2 in DRAM is replacedby D2'.

Thereafter, data D2' rewritten by the external write data D istransferred to that region of the SRAM to which access is requested bythe CPU. Therefore, the region of the SRAM which has stored data D1' isrewritten by data D2' (FIG. 52C). Therefore, data rewritten by data D2is stored in that region of the SRAM to which access is requested by theCPU. After the completion of this transfer, DRAM is set to the prechargestate. At this state, SRAM can be accessed (see FIG. 52D).

Thereafter, transfer of data D1 stored in the latch to region D1 of DRAMis carried out. Transfer operation of the data D1' latched in latch 1811to DRAM array will be described.

FIG. 53 is a diagram of signal waveforms showing data transfer operationfrom SRAM to DRAM. Referring to FIG. 53, at time t1, an array accessrequest is made, and an address for designating a region in which dataD1' is to be stored is applied (for example, output from a tag memory).From t1 to t6, selection of a DRAM word line DWL, detection andamplification of memory cell data connected to the selected word lineare carried out in the same manner as shown in FIG. 51, and data onlocal I/O lines and on global I/O lines are established.

At time t7, transfer control signal φTLD is generated, and gate circuit1812 shown in FIG. 49 is opened. Namely, referring to FIG. 50,transistors T105 and T106 are turned on, and data latched in latchcircuit 1811 is transmitted to global I/O line GIOa and *GIOa. Datatransmitted to global I/O line GIOa (*GIOa) is transmitted to DRAM bitline DBL (*DBL) selected by a column selecting line CSL through a localI/O line LIOa (*LIOa). The transfer operation of data D1 from SRAM toDRAM is completed.

During transfer operation of data latched in latch circuit 1811 to DRAM(copy back operation), SRAM can be arbitrarily accessed. Morespecifically, the address applied to DRAM at this time is independentfrom the address applied to SRAM. (Since simultaneous transfer of 16bits×4 bits of data is carried out in DRAM at the copy back transfer),selecting operation can be done by SRAM column decoder in accordancewith a SRAM address signal Ac. At this time, since transfer controlsignal φTDS is at "L" and transfer control signal φTSL is also at "L",gate circuits 1815 and 1810 are both closed, and therefore, DRAM arrayis separated from SRAM array. SRAM array can be independently accessedwithout any influence of data transfer operation to the DRAM array.

FIG. 54 schematically shows data transfer operation from latch circuitto DRAM. Referring to FIG. 54A, data D1' is stored in the latch. In theDRAM, a word line (hatched portion) including a region for storing dataD1 is selected in accordance with an external address (applied from atag memory or the like).

Thereafter, data D1' latched in the latch is transferred to the regionD1 included in the selected word line, and data in this region ischanged to D1' (FIG. 54B). Consequently, data transfer from the latch tothe DRAM is completed.

The operation at a cache miss reading will be described. The operationin the cache miss reading is the same as the operation of the cache misswriting described above, except that the DRAM write enable signal AWDEis at "L" and the gate circuit 1813 is closed. In this operation, asshown in the diagram of waveforms of FIG. 55, word lines SWL and DWL areselected in the SRAM array and the DRAM array. Data of the SRAM array islatched by latch circuit 1811, and data from the DRAM array istransmitted to SRAM bit line SBLa (*SBLa) at time t7. After the datatransfer to SRAM at t7, precharging operation is not necessary in SRAM.Therefore, the transferred data can be immediately read. Namely, at atime of a cache miss, data writing operation and data reading operationcan be executed in the same cycle time. Data transfer operation fromlatch circuit 1811 to DRAM is the same as the operation at the time ofcache miss writing described above (see FIGS. 53 and 54).

Let us assume that data D1' is stored in that region of the SRAM arraywhich is designated by an address from the CPU, and that CPU requestsdata D2. At this time, DRAM and SRAM are at the standby state (FIG.56A).

If such a cache miss occurs, first a SRAM word line is selected in SRAM,and data D1' is transferred to the latch (latch circuit 1811). Inparallel to the latching operation, a word line (hatched portion)including data D2 is selected in the DRAM in accordance with an addressfrom the CPU (FIG. 56B).

Thereafter, data D2 included in the selected word line of the DRAM istransferred to the region of the SRAM in which the data D1' has beenstored, through amplifier circuit 1814 and gate circuit 1815. The latchcircuit 1811 keeps the data D1' latched. In the SRAM, data D2 which hasbeen transferred from DRAM can be immediately read (FIG. 56C).

After the data transfer from DRAM to SRAM, the DRAM is temporarily setto a precharge state, so as to replace data D1 by data D1' The regionstoring the data D1 is that region in which the data D1' which has beenstored in the SRAM is to be stored (FIG. 56D).

After the completion of precharging in the DRAM, a word line (hatchedportion) including data D1 is selected (FIG. 56E). In the word lineselecting cycle (array active cycle), the SRAM can be externallyaccessed.

To the region storing data D1 included in the selected word line of theDRAM, the data D1' which has been latched in the latch (latch circuit1811) is transferred. Consequently, data D1 in the DRAM is rewritten bythe data D1' which has been stored in the SRAM (FIG. 56F).

The externally applied address means, in the DRAM, an address from theCPU when a word line is selected in data transfer to SRAM. It means anaddress from, for example, an external tag memory, when a word line isselected for receiving data from the latch circuit.

FIG. 57 schematically shows a further structure of a bi-directional datatransfer device. FIG. 57 shows a bi-directional transfer gate circuitrelated to transfer of 1 bit of data in the bi-directional data transferdevice, as does FIG. 49. In FIG. 57, the same or corresponding portionsare denoted by the same reference numerals as in FIG. 49.

Referring to FIG. 57, the bi-directional transfer gate circuit includes,in addition to the structure of the bi-directional data transfer circuitshown in FIG. 49, a gate circuit 1817 which is provided between SRAM bitline pair SBLa, *SBLa and internal write data transmitting lines DBW,*DBW. Gate circuit 1817 is opened in response to an output SAY of SRAMcolumn decoder and to SRAM write enable signal SWDE. SRAM write enablesignal SWDE is generated at data writing to SRAM, and it is generatedwhen the write enable signal W# is at an active state, that is, "L",either at a cache hit or at a cache miss.

FIG. 58 shows an example of a specific structure of the bi-directionaltransfer gate circuit shown in FIG. 57. Referring to FIG. 58, gatecircuit 1817 includes a gate circuit 1817a for transmitting write dataon internal write data bus line DBW to SRAM bit line SBLa, and a gatecircuit 1817b for transmitting write data on write data bus line *DBW toSRAM bit line *SBLa. Gate circuit 1817a includes an n channel MOStransistor T141 which is turned on in response to the output SAY fromSRAM column decoder, and an n channel MOS transistor T140 which isturned on in response to SRAM write enable signal SWDE.

Gate circuit 1817b includes an n channel MOS transistor T143 which isturned on in response to the output SAY of SRAM column decoder, and an nchannel MOS transistor T142 which is turned on in response to SRAM writeenable signal SWDE. Both of the gate circuits 1817a and 1817b transmitdata on internal data bus lines DBW and *DBW to SRAM bit lines SBLa and*SBLa when the SRAM column decoder output SAY and SRAM write enablesignal SWDE are at the active state, that is, "H". Other structures arethe same as those shown in FIG. 50. Data transfer from DRAM to SRAM incache miss writing will be described with reference to FIG. 59, which isa diagram of signal waveforms.

The operation up to the time t7 is the same as that of thebi-directional transfer gate circuit shown in FIGS. 49 and 50. Data fromthe SRAM has been latched in the latch circuit 1811, and memory celldata from the DRAM array has been transmitted to global I/O line GIOa(*GIOa).

When transfer control signal φTDS rises to "H" at time t7, amplifiercircuit 1814 and gate circuit 1815 operate to amplify signal potentialson the global I/O lines GIOa and *GIOa and transmit the same to SRAM bitline pair SBLa and *SBLa. In parallel to this transfer operation, DRAMwrite enable signal AWDE rises to "H", gate circuit 1816 is opened, andwrite data on write data lines DBW and *DBW are transmitted to globalI/O lines GIOa and *GIOa. Consequently, write data is written to thememory cell selected in the DRAM array.

In parallel to the data transfer operation from the DRAM to the SRAM inresponse to transfer control signal φTDS, SRAM write enable signal SWDErises to "H", gate circuit 1817 (1817a, 1817b) is opened, and write dataon the write data bus lines DBW and *DBW are transmitted to SRAM bitlines SBLa and *SBLa. Consequently, signal potentials on the SRAM bitlines SBLa and *SBLa are established at signal potentials correspondingto the value of the write data.

The DRAM write enable signal AWDE and SRAM write enable signal SWDE maybe generated at any time after the generation of transfer control signalφTDS and after the start of data transfer operation from DRAM to SRAM.

In the structure of the bi-directional transfer gate circuit shown inFIGS. 57 and 58, write data on the internal write data bus line isdirectly transmitted to SRAM bit lines SBLa and *SBLa through the gatecircuit 1817. Therefore, when writing to data in the SRAM is effected bytransferring write data from internal data bus lines DBW and *DBW toDRAM, and then transmitting write data from DRAM to the SRAM, and if theaccess time of DRAM is relatively short, there is a possibility thatdata rewritten by the write data cannot be surely transmitted to theSRAM, since there is not always sufficient time for transmitting writedata through such path. In that case, a structure in which data isdirectly transmitted from internal write data bus lines DBW and *DBW tothe SRAM bit lines SBLa and *SBLa through gate circuit 1817 enablestransmission of data which is surely rewritten by the write data to theSRAM.

FIGS. 60A through 60D schematically show data transfer operation fromthe DRAM to the SRAM by the bi-directional transfer gate circuit shownin FIGS. 57 and 58. The data transfer operation will be brieflydescribed with reference to FIGS. 60A through 60D.

As in FIG. 60A, let us assume that CPU requests rewriting of data D2.DRAM and SRAM are both at the precharge state (FIG. 60A).

Referring to FIG. 60B, a word line (hatched portion) including data D2is selected in the DRAM, while in the SRAM, data of the region includingdata D1' are transmitted to the latch. The data D1' is not to berewritten but it should be transferred to that region of the DRAM inwhich the data D1 is to be stored.

Referring to FIG. 60C, while data D2 of the DRAM is being transferred toa corresponding memory cell of the SRAM, write data D is transferred tothe region of the DRAM to which data D2 is to be stored, and also tothat region of the SRAM to which data D1 is to be stored. Consequently,data D2 in the DRAM and in the SRAM are changed to data D2' which hasbeen rewritten by the write data D. Namely, in parallel to data transferfrom the DRAM to SRAM, write data D is written to SRAM, and data writingis carried out in DRAM.

Referring to FIG. 60D, the DRAM is returned to a precharge state, so asto transfer the latched data D1' to the region for storing the data D1in the DRAM. In this state, CPU can access SRAM.

Transfer operation of the data D1' latched in the latch (latch circuit1811) to data D1 storing region of the DRAM is the same as thatdescribed with reference to FIG. 54. Therefore, it is not repeated.

In the bi-directional data transfer circuit shown in FIGS. 57 and 58,gate circuits 1816 and 1817 are both opened in cache miss writing.Therefore, the same operation as the data transfer operation describedwith reference to the bi-directional transfer gate circuit shown inFIGS. 49 and 50 is carried out, namely, only the data transfer operationschematically shown in FIGS. 56A to 56F is carried out. Therefore, thedescription thereof is not repeated.

By providing such a gate circuit 1817 as described above, even if thereis not a sufficient time for rewriting data in the DRAM by write data Dand then transmitting the rewritten data to the SRAM, data in the SRAMcan be surely rewritten by the write data D.

A so-called "write through mode" is available in the above describedbi-directional data transfer device. In the "write through mode", datawritten to the SRAM is also written to the corresponding memory cell ofthe DRAM at that time during cache access. Namely, if the abovedescribed cache miss writing operation is executed at a cache hit whendata exists in the SRAM, the write through is enabled. In cache misswriting operation when data does not exist in the cache, the abovedescribed cache miss writing operation may be done without modificationfor directly writing data to the DRAM array.

When the DRAM is to be directly accessed, data can be directly writtento the DRAM by activating only the DRAM write enable signal AWDE. Whendata is to be written only to the SRAM at a time of a cache hit and itis not necessary to execute the write through mode operation, only theSRAM write enable signal SWDE is set to the active state.

When data transfer is carried out by using the data transfer deviceshown in FIGS. 49 and 50 or FIGS. 57 and 58, only one precharge periodis necessary in the DRAM for receiving the latched data, and thereforedata transfer can be carried out at a high speed between the SRAM andthe DRAM. In the conventional copy back and block transfer mode cycles,the SRAM cannot be accessed before the completion of block transfer.However, by using the high speed copy back mode, data transfer from theDRAM to the SRAM is carried out in the first data transfer cycle,namely, the conventional block transfer is carried out at first, so thatafter the data transfer to the SRAM, the SRAM can be directly accessed.Therefore, a semiconductor memory device containing a cache havinghigher speed of operation can be realized.

In the bi-directional data transfer device, rewriting of data to SRAM iscarried out in parallel to data transfer. Therefore, operations in cachemiss reading and cache miss writing can be executed in the same cycletime.

In the foregoing, the high speed copy back mode is applied to datatransfer between SRAM array and DRAM array at a cache miss in asemiconductor memory device containing a cache, as an example. However,high speed exchange of data is also made possible when data aretransferred between two memory cells such as a normal SRAM array and aDRAM array, and efficiency in data transfer can be significantlyimproved. Namely, the bi-directional data transfer device can be appliednot only to a semiconductor memory device containing a cache such asshown in FIG. 32 but also to a semiconductor memory device having ageneral high speed memory and a memory of large capacity, as a datatransfer device between the high speed memory and large capacity memory.

(c) Data Transfer Between DRAM Array and SRAM Array with Reduced CurrentConsumption

(i) In the arrangement with clamping transistors as shown in FIGS. 24and 30, data can be transferred between DRAM array and SRAM arraybecause of the reduced logical swing of the potentials of SRAM bitlines. This clamping transistor arrangement can be expanded moregenerally to achieve high speed data transfer operation with lesscurrent consumption. Now, data transfer operation with modified clampingtransistor arrangement will be described with reference to FIGS. 61through 70.

FIG. 61 shows an array structure for fast data transfer with reducedcurrent consumption. The arrangement of FIG. 61 is the same as that ofFIG. 8 except that clamping circuits CRS are provided for respectiveSRAM bit line pairs SBL, and clamping circuits CRD for clamping DRAM IOlines are provided. The SRAM clamping circuit has the same constructionas that of FIG. 21, that is, diode-connected transistors provided foreach SRAM bit line.

DRAM clamping circuits CRD includes a clamp circuit CRDa provided forthe global IO line pair GIOa and a clamping circuit CRDb provided forthe global IO line pair GIOb. Clamping circuits may be provided for thelocal IO line pairs LiOa and LIOb. The clamping circuits may be providedboth for the global IO line pairs GIOa and GIOb and for the local IOline pairs LIOa and LIOb.

The SRAM array of FIG. 61 is shown having one Word line per one row ofSRAM cells, but it may have the multiplicate word line arrangement of aplurality of word lines per one row of SRAM cells as shown in FIG. 24.

The bidirectional data transfer gate circuit 3 includes bidirectionaltransfer gates BIGa and BIGb provided between SRAM bit line pairs SBLand the global IO line pairs GIOa and GIOb. The bidirectional transfergates BIGa and BIGb carry out data transfer between SRAM bit line pairsand the global IO lines GIOa and GIOb in response to data transferinstructing signals DIS and DIA. The signal DIS instructs data transferfrom DRAM array to SRAM array. The signal DIA instructs data transferfrom SRAM array to DRAM array.

SRAM clamping circuit CRS is enabled and disabled in response to asignal/DTS which is an inversion signal of the signal DTS. DRAM clampingcircuits CRD is enabled and disabled in response to a signal/DTA whichis an inversion signal of the signal DTA.

In data transfer from DRAM array to SRAM array, the transfer instructingsignal DTS is activated to be "M" to disable the SRAM clamping circuitCRS to inhibit the bit line clamping in SRAM array. In data transferfrom SRAM array to DRAM array, the transfer instructing signal DTA isactivated to be "H" to disable the clamping circuits CRDa and CRDb(and/or CRDa' and CRDb').

FIG. 62 shows a construction related to a data transfer gate of FIG. 61.In FIG. 62, the global IO line pair LIO and the global IO line pair GIOare shown combinedly as DRAMIO line pair DIO. The global IO line pair isprovided only for one memory block while the global IO line pair isprovided commonly for the memory blocks in a column block (see FIGS. 7and 8). Therefore, the clamping circuit CRD is preferably provided atleast for the global IO line pair GIO. The arrangement of FIG. 60includes the block selection gates IOGa and IOGb. However, the global IOline pair GIO and the local IO line pair LIO are combinedly shown asDRAMIO line pair DIO. Accordingly, block selection gate IOG and columnselection gate CSG of FIG. 60 is combinedly shown as a selection gateSG.

Only the DRAMIO line pair DIO connected to one bidirectional transfergate BIG is shown in FIG. 62, and therefore the column selection signalCSL transferred on the column selecting line CSL is shown selecting oneselection gate SG in FIG. 62.

DRAM bit line pair DBL includes bit lines DBL and *DBLa, and SRAM bitline pair SBL includes bit lines SBLa and *SBLa. DRAM bit lines DBLa and*DBLa representatively show pairs of bit lines DBLaO, *DBLaO throughDBLan, *DBLan. SRAM array also includes word lines SWLo through SWLn,and DRAM array includes word lines DWLo through DWLp.

SRAM clamping circuit CRS includes n channel MOS transistor SQ70 for theSRAM bit line SBLa and n channel MOS transistor SQ80 for the SRAM bitline *SBLa. The transistors SQ70 and SQ80 receive the inversionsignal/DIS at their gates.

DRAM clamping circuit CRD includes n channel MOS transistor DQ70 forDRAMIO line DIOa and n channel MOS transistor SQ80 for DRAMIO line*DIOa. The inversion signal/DTA is applied to the gates of thetransistors DQ70 and DQ80.

(ii) Various constructions can be applied for the data transfer gate.First, the bidirectional transfer gate as shown in FIG. 63 isconsidered. The gate of FIG. 63 is the same as the gate of FIG. 44except for the naming of the components and the signal. Therefore, nodetailed explanation is described of the gate of FIG. 63. Now, anoperation in transferring data from DRAM array to SRAM array withreference to FIG. 63 showing the operating waveform diagram therefor.Data transfer from DRAM array to SRAM array is effected in the cachemiss where the signal CI is active at "H".

Before time t1, the precharge instructing signal φEQ is active at "H",and therefore, the equalizing transistors TEQ equalize the senseamplifier driving signal lines SAN and /SAP to the precharge potentialof Vcc/2. The DRAM bit line pair DBL (bit lines DBLa, *DBLa) areprecharged to the intermediate potential of Vcc/2 by theprecharge/equalize circuit DE.

DRAMIO lines DIOa and *DIOa are precharged to "H" at the potential levelof Vcc-Vth by the clamping circuit CRD. SRAM bit liens SBLa and *SBLaare precharged to "H" at the potential level of Vcc-Vth by the clampingcircuit CRS.

At time t1, the precharge instructing signal φEQ falls to "L" to disablethe equalizing transistors TEQ and precharge/equalize circuit DE, whichcompletes the precharging of the sense amplifier driving signal linesSAN and /SAP, and the DRAM bit lines DBLa and *DBLa. DRAM bit lines DBLaand *DBLa, and the sense amplifier driving signal lines SAN and /SAP arebrought into a floating state at the intermediate potential Vcc/2.

Then, row decoder 14 (see FIG. 9) carries out a row selection operationin accordance with an externally applied address.

After a certain time has elapsed from the time t1, one word line DWL isselected in DRAM array, and the potential of the selected word line DWL(one of the word lines DWLo to DWLp) rises to "H". DRAM memory cells DMCconnected to the selected word line DWL are connected to associated DRAMbit lines DBLa (or *DBLa) whose potentials are changed in accordancewith data of the associated memory cells.

FIG. 64 shows the DRAM bit line potential change when a memory cellstoring "H" data is selected.

At time t2, a sense amplifier activating signal SANE rises from theground potential to the operating power supply Vcc, to turn on thetransistor TR2 in the sense amplifier activating circuit SAK.Consequently, the sense amplifier driving signal SAN falls from theintermediate potential level Vcc/2 to the ground potential, to activatethe N sense amplifier part in the DRAM sense amplifier DS. Potential ofthe bit line of a lower potential in a DRAM bit line pair is dischargedto the ground potential level Vss.

At time t3, the sense amplifier activating signal/SAPE falls from theVcc level to Vss level, to turn the transistor TR1 in the senseamplifier activating circuit SAK. Responsively, the sense amplifierdriving signal/SAP rises from the intermediate potential Vcc/2 to thesupply potential Vcc. Then, D sense amplifier part in DRAM senseamplifier DSA is activated to boost the potential of a bit line of ahigher potential in the pair to the supply potential level Vcc.

At time t4, the column selection signal CSL is generated by the decodingin the column decoder 15 (see FIG. 9). Then, a selected gate SGi is makeconductive to connect and associated DRAM bit line pair (DBLia, *DBLia)to DRAMIO line pair DIO (DIOa, *DIOa). DRAM sense amplifier DSA has alarger driving ability than the current supplying ability of theclamping circuit CRD. Consequently, the potentials of DRAMIO line paircorrespond to the potential levels of "H" and "L" amplified by the senseamplifier DSA.

In this operation, "L" level of DRAMIO line pair DIO is slightly higherthan the ground potential because the clamping circuit CRD suppliescurrent flow to implement the pull-up function. The "L" level potentialis determined by the current driving abilities of the clampingtransistors SQ70 and SQ80, the transistor of the selection gate SGi andthe discharging transistors (n channel MOS transistors; see FIG. 8) inDRAM sense amplifier DSA. The selection gate SGi has a relatively highresistance, and the logical swing of the DRAMIO line DIOa (*DIOa) isdetermined by the ratio of on resistances of the clamping transistorDQ70 (or DQ80) and the transistor of the selection gate SGi. DRAM bitline has substantially a full logical swing of Vcc level by DRAM senseamplifier DSA.

DRAMIO line DIOa (or DIOa) has a greater capacitance than DRAM bit lineDBLa (or *DBLa). Thus, although "L" level potential of DRAM bit lineDBLa (or *DBLa) rises slightly when the column selection signal CSLirises; DRAM bit line is ensurely discharged to the ground level by DRAMsense amplifier DSA driving the small capacitance of DRAM bit line. Thissituation is analogous to the data reading out operation in an ordinaryDRAM in which internal data transmitting lines are precharged to "H"level. Therefore, even if the clamping transistors DQ70 and DQ80 are inan on-state, the current flow from the clamping transistors DQ70 andDQ80 cannot destruct data in a DRAM memory cell.

In SRAM array, SRAM row decoder 21 (see FIG. 9) carries out rowselection operation at time ts1 to select a SRAM word line SWL (one ofSRAM word lines SWLO to SWLm), and raises the potential of the selectedSRAM word line SWL.

Row selection in DRAM and row selection in SRAM are carried outasynchronously with each other. Data of SRAM cells connected to theselected SRAM word line SWL are transferred to associated SRAm bit linepair SBL. Consequently, the potentials of SRAM bit lines SBLa and *SBLachange from the clamping potential of Vcc-Vth to the potentialscorresponding to the transferred data.

At time t5, the data transfer instructing signal DTS instructing datatransfer from DRAM array to SRAM array rises to "H". Before the time t5,data of selected DRAM cell has been transferred onto DRAMIO lines DIOaand *DIOa, and SRAM cell has been connected to SRAM bit line pair SBL.Then, the transfer circuit TGS shown in FIG. 63 is activated to transferdata on DRAMIO lines DIOa and *DIOa to SRAM bit lines SBLa and *SBLa inresponse to the signal DIS.

In this operation, the clamping transistors SQ70 and SQ80 are made beingturned off. Thus, "H" and "L" levels of SRAM bit lines SBLa and *SBLacorrespond to the potential levels supplied by the transfer gate TGS.

The relationship between the time ts1 and the times t1 through t5 isarbitrary as far as the time t5 at which the signal DIS is activated isalter than both the time when the column selection signal CSLi isgenerated and the potentials of DRAMIO line pair DIO are asserted andthe time ts1 when selection of SRAM word line SWL is carried out. Thesignal DIA instructing data transfer from SRAM array to DRAM array ismaintained at "L" during this data transfer operation.

At time t6, the selected DRAM word line DWL has its potential fallen to"L", and the transfer instructing signal DIS falls to "L". Responsively,the clamping circuit CRS, for SRAM bit line pair SBL is activated againto raise the "L" potential level of SRAM bit line SBLa (or *SBLa).

At time t7, the sense amplifier driving signals SAN and /SAP both returnto the intermediate potential level Vcc to release the latching by DRAMsense amplifier DSA. Then, DRAMIO lines DIOa and *DIOa have thepotential returned to "H" of Vcc-Vth by means of DRAM clamping circuitCRD for DRAMIO line pair DIO. Thereafter, the column selection signalCSLi falls to "L" to isolate DRAM bit line pair from DRAMIO line pair.

In SRAM, the potential of SRAM word line SWL falls to "L" at the timets2, to complete the data transfer cycle for transferring data from DRAMarray to SRAM array.

Clamping circuits CRD and *CRS operate to reduce the logical swing ofassociated signal lines to establish the signal potentials thereon athigh speed, resulting in fast data transfer.

If clamping circuits CRS and CRD are maintained active during the datatransfer operation, a current flow flows from the clamping transistorSQ70 (or SQ80) for SRAM bit line through an output driving transistorincluded in the transfer circuit TGS into the ground level, resulting inincreased current consumption. Data transfer is made on a unit of pluralbits such as 16 bits in the CDRAM of the invention, and therefore thepenetrating current flow from the clamping transistors provides asignificant value to degrade the low current consumption performance.Inhibition of the clamping by the clamping circuit CRS for SRAM bit linepair receiving the transferred data reduces significantly thepenetrating current flow.

In DRAM transferring data, clamping circuit CRD is maintained operating.The clamping circuit CRD implements pull-up function. The current supplyabilities of the clamping transistors DQ70 and DQ80 is small. Theon-resistance of the selection gate SGi is relatively large. The currentflow from the clamping transistor DQ70 or DQ80 is discharged by DRAMsense amplifier DSA. DRAM bit line potentials are made at Vcc and Vsslevels by DRAM sense amplifier DSA while "L" level of DRAMIO line DIOaor *DIOa is slightly raised to a level determined by the ration ofon-resistance of the clamping transistor DQ70 (or DQ80) to on-resistanceof the selection gate SGi and the discharging transistor in DRAM senseamplifier DSA.

Bidirectional transfer gate BTG has sufficiently larger current drivingability than the discharging ability (or latching ability) of thetransistor in SRAm memory cell. Therefore, when the bidirectionaltransfer gate BTG operates, large current flow is caused from theclamping transistor SQ70 or SQ80 into a driving transistor in thetransfer gate BTG. The current flow becomes large when a block of datais transferred simultaneously. This large current flow is saved bydeactivation of SRAM clamping circuit CRS.

In the data transfer from DRAM to SRAM as described above, the clampingcircuit CRS for SRAM bit line pair SBL is inhibited from clamping thepotential in synchronization with the data transfer instructing signalDTS. However, there is a possibility that a column current which flowsfrom the clamping transistor SQ70 or SQ80 into SRAM memory celltransistor may be caused when SRAM word line SWL has the potential risento "H" and SRAM bit lines are subjected to the potential clamping. Inorder to reduce this column current, the clamping operation of the SRAMclamping circuit CRS is inhibited in synchronization with the selectionof an SRAM word line. This construction can be implemented by applying alogical product signal of the data transfer instructing signal for datatransfer from DRAM to SRAM and an SRAM word line driving signal SWL.Data transfer from DRAM to SRAM is carried out in a cache miss, and thedata transfer instructing signal DTS can be asserted prior to theselection of an SRAM word line.

Now, data transfer from SRAM to DRAM will be described with reference toFIG. 65 showing operation waveforms therefor.

In DRAM, the same operation as that of DRAM to SRAM data transferdescribed with reference to FIG. 64 is carried out from the time t1 tillthe time t4. In SRAM, similarly, SRAM word line SWL is selected to havethe potential risen at the time ts1.

After the times t4 and ts1, the transfer instructing signal DTA allowingdata transfer from SRAM to DRAM is activated for a predetermined periodfrom the time t5. The transfer circuit TG as shown in FIG. 63 isactivated to transfer the signal potentials appearing on SRAM bit linesSBLa and *SBLa to DRAMIO lines DIOa and *DIOa in response to thetransfer instructing signal DTA. DRAMIO lines DIOa and *DIOa have thepotentials of "H" at Vcc level and "L" at Vss (ground) level by thelarge driving ability of the transfer circuit TGA. The signal potentialson DRAMIO lines DIOa and *DIOa are transferred onto the selected DRAMbit lines DBLa and *DBLa through the selected selection gate SGi. Thetransfer circuit TGA has a driving ability much larger than the latchingability of DRAM sense amplifier DSA, and therefore DRAM bit lines DRAMbit lines DBLa and *DBLa have the signal potentials corresponding to thedata transferred from the selected SRAM memory cell.

DRAM clamping circuit CRD has its clamping operation inhibited at thetime t5 in response to the signal DTA, and the transistors DQ70 and DQ80are turned off. Consequently, no current flows from the clampingtransistors DQ70 and DQ80 into a driving transistor in the transfercircuit TGA, reducing the current consumption.

At the time t6, the data transfer instructing signal DTA falls to "L",and at substantially the same timing, DRAM word line DWL has thepotential fallen to "L". The falling of DRAM word line potentialcompletes the data writing for a selected DRAM cell.

The clamping circuit CRD is activated again to raise the low levelpotential of DRAMIO line DIOa or *DIOa by the clamping operation. Theactive DRAM sense amplifier DSA maintains "H" and "L" levels of DRAM bitlines DBLa and *DBLa.

At time t7, the sense amplifier driving signals SAN and/SAP aredeactivated, and the column selection signal CSLi rises, and DRAMreturns to the precharge state.

In SRAM, SRAM word line SWL has the potential fallen to "L" at the timets2 to isolate SRAM memory cell from SRAM bit line pair.

The SRAM bit lines SBLa and *SBLa have the "H" potential leveldetermined by the clamping transistors SQ70 and SQ80.

As described above, inhibition of the clamping operation of DRAMclamping circuit CRD during data transfer from SRAM to DRAM prevents thegeneration of discharging current flow (penetrating current flow)through the driving transistor included in the transfer circuit TGAhaving a large driving ability, resulting in reduced currentconsumption.

(iii) Second Data Transfer Arrangement with Reduced Current Consumptionat a High Speed

FIG. 66 shows another construction of the bidirectional transfer gatecircuit BTG. By use of the construction of FIG. 66, data transfer fromSRAM to DRAM can be carried out in parallel with the data transfer fromDRAM to SRAM.

In FIG. 66, the bidirectional transfer gate BTG includes a drive circuitTGAO for transferring data on SRAM bit line SBLa (or *SBLa) in responseto a data transfer allowing signal DTAO, a buffer BU2 for buffering anoutput of the drive circuit TGAO, and a drive circuit TGA1 fortransferring are output of the buffer BU2 onto DRAMIO line DIOa (or*DIOa) in response to a data transfer allowing signal DTAI.

The data transfer allowing signals DTAO and DTAI are generated atdifferent timings from each other.

The transfer gate BTG further includes a drive circuit TGSO responsiveto a data transfer allowing signal DISO for transferring data on theDRAMIO line DIOa (or *DIOa), a buffer BU1 for buffering an output of thedrive circuit TGSO, and a drive circuit TGSI for transferring an outputof the buffer BU1 onto the SRAM bit line SBLa (or *SBLa) in response toa data transfer allowing signal DTSI. Transfer allowing signals DTAO andDTSO are generated at substantially the same timing and the transferallowing signals DTAI and DTSI are generated at substantially the sametiming, if data transfer from SRAM to DRAM as well as data transfer fromDRAM to DRAM are carried out.

In the construction of FIG. 66, the transfer allowing signals DTAO andDISO are first generated. Prior to the generation of these signals DTAOand DISO, the name operation as shown in FIGS. 64 and 65 is carried out.When the transfer allowing signals DISO and DTAO are generated, data ofa selected SRAM memory cell is transferred to the buffer Bu2 to bebuffered therein. Data of a selected DRAM memory cell is transferred tothe buffer BU1 to be buffered thereat. After the outputs of the buffersBU1 and BU2 are settled, the data transfer allowing signals DTAI andDISI are made active. Responsively, the output data of the buffer BU1 istransferred to SRAM bit line SBLa (or *SBLa) through the drive circuitTGSI.

The output data of the buffer BU2 is transferred to dram bit line DBLa(or *DBLa) through the drive circuit TGAI and DRAMIO line DIOa (or*DIOa). The transfer allowing signals DTAO and DTAI, and DISO and DISIcan be considered as two shot pulsed signals DIA, and DIS respectively,in FIGS. 64 and 65. According to this construction, data transfer fromSRAM to DRAM and data transfer from DRAM to SRAM can be carried out inparallel with each other, resulting in efficient data transfer.

The timings for generating the signals DTAO, DTAI, DISO and DISI may bedetermined such that data transfer from SRAM to DRAM and data transferfrom DRAM to SRAM are carried out in a partially overlapped manner.

SRAM bit line SBLa (or *SBLa) is provided with a clamping transistorSQ75 and DRAMIO line DIOa (or *DIOa) is provided with a clampingtransistor DQ85 in order to implement fast data transfer with lesscurrent consumption. The transistor SQ75 provides the SRAM clampingcircuit CRS, and the clamping transistor DQ75 provides the DRAM clampingcircuit CRD.

In this construction, the clamping circuit CRS has the clampingoperation inhibited by a signal /DTSI of an inversion of the signal DTSIin order to prevent current from flowing into a driving transistor inthe drive circuit TGSI from the clamping transistor SQ75 when SRAM bitline SBLa (or *SBLa) receives data transferred from DRAM. The transistorSQ75 receives the signal /DTSI at the gate. Likewisely, DRAM clampingcircuit CRD has the clamping operation inhibited by the signal /DTAI ofan inversion of the signal DTAI. The transistor DQ85 receives the signal/DTAI at the gate.

(iii) Third Embodiment for First Data with Less Current Consumption

FIG. 67A shows a further another construction of the bidirectional datatransfer gate, and FIG. 67B shows a detailed construction of thetransfer gate of FIG. 67A. The construction of the bidirectional datatransfer gate is the same as that shown in FIGS. 49 and 50. In FIGS. 67Aand 67B, like components have like reference numerals allotted thereto,and detailed explanation on the construction of FIGS. 67A and 67B isomitted.

The signal DTS corresponds to the signal φTDS, and the signal DTAcorresponds to the signal φTLD, and the signal DTL corresponds to thesignal φTSL.

SRAM bit line pair SBL is provided with the SRAM clamping circuit CRSoperable in response to the signal /DTS, and DRAMIO line pair DIO isprovided with the DRAM clamping circuit CRD operable in response to thesignal /DTA. Now, the operation of the gate of FIGS. 67A and 67B will bedescribed with reference to FIGS. 68 and 69 showing the operatingwaveforms thereof.

First, data transfer from DRAM array to SRAM array will be describedwith reference to FIG. 68. In this data transfer operation,substantially the same operation as that shown in FIG. 55 except for thecontrol of the clamping circuits CRD and CRS. Thus, only the control onthe clamping circuits CRD and CRS will be described.

At time t5, the data transfer control signal DIS rises to "H" to inhibitthe clamping operation of the clamping circuit CRS. The SRAM bit linesSBLa and *SBLa are released from the clamping by the clamping circuitCRS, and have the potentials corresponding to the potential levelssupplied from the amplifier circuit 1814. Due to the deactivation of theclamping circuit CRS, a current flowing path from the clamping circuitCRS through the transistors T120, T112 and T113 or through thetransistors T121, T116 and T117 of FIG. 67B is cut off.

At time t6, DRAM word line DWL has the potential fallen to "L", and thetransfer control signal DIS falls to "L" substantially at the sametiming. Responsively, SRAM clamping circuit CRS is activated to clampthe potentials of SRAM bit lines SBLa and *SBLa or to raise "L" levelpotential of SRAM bit line pair SBL. In this state, the transistors T120and T121 of the gate 1815 are turned off in response to the falling ofthe signal DTS, and current from the clamping circuit CRS does not flowinto the bidirectional gate circuit BTG to the ground.

After the time t6 at which the transfer control signal DIS falls to "L",DRAM array and SRAM array are isolated from each other, and SRAM arraycan be accessed externally so that data transferred from DRAM array canbe read out at a high speed.

Now, the operation of data transfer from the latch circuit 1811 to DRAMarray will be described with reference to FIG. 70. Data transferoperation per se is the same as that shown in FIG. 53. Thus, theoperation of the clamping circuit CRD will be described.

At the time t5, the transfer control signal DTA rises to "H". In thisdata transfer cycle, the signals DTS and DTL both are maintained at "L".In response to the transfer control signal DTA, the gate circuit 1812 ofFIG. 67A or the transistors T105 and T106 turn on to transfer the datalatched in the latch circuit 1811 to DRAMIO line pair DIO. DRAM clampingcircuit CRD is deactivated to have its clamping operation inhibited.DRAMIO lines DIOa and *DIOa have the potentials of "H" and "L"corresponding to the data latched in the latch circuit 1811.

Because of the transfer control signal DTA at "H", the clampingtransistors DQ70 and DQ80 (see FIG. 62) are turned off, to cut off theclamping current flowing path through DRAMIO line DIOa, the transistorT106 and the inverter circuit HA13 or through DRAMIO line *DIOa, thetransistor T105 and the inverter circuit HA12.

At the time t6, DRAM word line DWL has the potential fallen, and thetransfer control signal DTA falls to "L" substantially at the sametiming. DRAM clamping circuit CRD is activated again to raise "L" levelpotential of DRAMIO line pair DIO.

At the time t7, the memory cycle of DRAM is completed, and successivelythe column selection signal CSLi falls to "L". DRAMIO line pair DIO hasthe potential levels determined by the DRAM clamping circuit CRD.

In this data transfer cycle, the transfer control signals DIS and DILboth are maintained at "L". DRAM array is isolated from SRAM array. DRAMaddress and SRAM address can be designated independently of each other.Thus, in the data transfer to DRAM array from the latch circuit 1811SRAM can be accessed externally to have an SRAM memory selectedindependently of the data transfer operation. More specifically, inSRAM, a word line SWL is selected according to an external access at thetime t1. SRAM bit line pair SBL has the potential levels changed fromthe "H" potential levels clamped by SRAM clamping to the levelscorresponding to data of a selected SRAM cell, and an access to theselected SRAM cell is carried out.

At the time ts4, SRAM word line SWL has the potential fallen to "L", andSRAM bit lines SBLa and *SBLa have the potentials clamped by SRAMclamping circuit CRS.

As described above, inhibition of clamping operation of DRAM clampingcircuit CRD in the data transfer to DRAM array to the latch circuit 1811prevents the clamping current of the clamping circuit CRD from flowinginto a drive transistor (discharging transistors of the invertercircuits HA12 and HA13 of FIG. 67B) to reduce current consumption indata transfer operation.

(iv) Modification of Clamping Circuit

FIG. 70 shows a modification of the clamping circuit. In FIG. 70, SRAMclamping circuit CRS includes p channel MOS transistor SQ71 having agate receiving the transfer control signal DIS for clamping thepotential of SRAM bit line SBLa, and p channel MOS transistor SQ81having a gate receiving the signal DTS for clamping the potential ofSRAM bit line *SBLa.

DRAM clamping circuit CRD includes p channel MOS transistor DQ71 havinga gate receiving the transfer control signal DTA for clamping thepotential of DRAMIO line DIOa, and p channel MOS transistor DQ81 havinga gate receiving the signal DTA for clamping the potential of DRAM IOline *DIOa. The transistors DQ71 and DQ81 may have their one conductionterminals coupled to receive Vcc potential level or Vcc/2 potentiallevel.

The operation of the clamping circuits of FIG. 70 is the same as that ofthe clamping circuit of FIG. 62. The clamping circuits of p channel MOStransistors provides the same effect as that of the clamping circuits ofn channel MOS transistors.

[Address Allottance]

In the CDRAM, DRAM address and SRAM address are set independently ofeach other. DRAM column decoder selects 16 column select lines in DRAMarray, while SRAM column decoder selects 1 column out of 16 columns.SRAM column decoder eventually selects a DRAM column in array access.Address allottance is described with reference to FIGS. 61 to 63.

FIG. 71 shows one example of connection of addresses to DRAM and SRAM.In the structure shown in FIG. 71, access to the DRAM array is carriedout through bi-directional transfer gate circuit or SRAM bit line pairsSBL of the SRAM array. In this structure, column selection signal CDfrom SRAM column decoder 22 is commonly used as a column selectingsignal for the DRAM array and the column selecting signal for the SRAMarray.

In FIG. 71, DRAM address buffer 252a receives external DRAM addressesAa0 to Aa9 and generates internal address int.Aa. DRAM row decoder 14decodes internal row address from internal address int.Aa, and generatesa word line driving signal DWL for selecting a word line from DRAMarray. DRAM column decoder 15 receives a portion of internal columnaddress from DRAM address buffer 252a, and generates a signal CSL forselecting a column selecting line from DRAM array. The remaininginternal column address from DRAM address buffer 252a is applied to abuffer 29. Buffer 29 receives internal column address from SRAM buffer252b and transmits the same to SRAM column decoder 22. When DRAM arrayis accessed, internal column address is not generated from SRAM buffer252b, as will be described in detail later. At that time, the buffer 29receives internal column address from DRAM address buffer 252a andtransmits the same to SRAM column decoder 22.

SRAM row decoder 21 receives internal row address from SRAM buffer 252b,and generates a SRAM word line driving signal SWL for selecting one rowfrom SRAM array. In accordance with the structure shown in FIG. 71, inthe data input/output structure of FIG. 33, the column selecting signalsDYi and DYj are equivalent to SRAM column selecting signals SYLi andSYLj.

FIG. 72 shows another example of a structure of address input/outputportion. In the structure shown in FIG. 72, instead of the buffer 29, amultiplexer 30 responsive to a cache hit designating signal CH and to aDRAM access designating signal CI for passing either an internal columnaddress from DRAM address buffer 252a or an internal column address fromSRAM address buffer 252b is provided. The cache signal CH and the DRAMarray access designating signal CI will be described in detail later.Only an outline will be described. When a cache hit designating signalCH is generated, access to SRAM array is permitted, and writing/readingof data by accessing to DRAM is inhibited. When DRAM array accessdesignating signal (cache access inhibiting signal) CI is generated,writing/reading of data by access to memory cells in DRAM array ispermitted.

Therefore, when the signal CH is generated, multiplexer 30 selects theinternal column address from SRAM address buffer 252b and transmits thesame to SRAM column decoder 22. When DRAM array access designatingsignal CI is generated, multiplexer 30 selects the internal columnaddress from DRAM address buffer 252a to transmit the same to SRAMcolumn decoder 22. In the structure shown in FIG. 72 also, SRAM columndecoder 22 is used for both column selections on DRAM array and on SRAMarray.

The structure for allotting addresses shown in FIGS. 71 and 72 are mereexamples. Structures for independently decoding internal column addressfor DRAM array and decoding internal column address for SRAM array maybe employed.

FIG. 73 shows a further example of the connection between SRAM array andinternal data transmitting line pair. In the structure shown in FIG. 33,a SRAM sense amplifier SSA is provided for each SRAM bit line pair SBL.In the structure shown in FIG. 73, one SRAM sense amplifier SSA isprovided for a plurality of SRAM bit line pairs SBL. A selecting gatecircuit 302 is provided for each SRAM bit line pair SBLa, *SBLa. Acolumn selecting signal CD is supplied to selecting gate circuit 302.The column selecting signal CD is generated from SRAM column decodershown in FIGS. 71 and 72. Internal data line pair includes an internalwrite data line 251a' for transmitting write data, and a read datatransmitting line 251b' for transmitting read data to an output buffercircuit. The internal write data transmitting line 251a' includes acomplementary data line pair DBW, *DBW. Complementary data from an inputbuffer circuit are transmitted to internal data lines DBW and *DBW. Theinternal write data line 251a' is connected to a write circuit 303.

The write circuit 303 includes cross coupled n channel MOS transistorsT301, T302, T303 and T304. Gates of transistors T302 and T303 areconnected to the internal data line DBW. Gates of transistors T301 andT304 are connected to internal data line *DBW. Complementary write datafrom write circuit 303 are transmitted to respective transmitting gatecircuits 302 through data lines DBWa, *DBWa. Transistors T301 and T302transmit a supply potential Vcc when they are on. Transistors T303 andT304 transmit ground potential Vss when they are on.

For example, let us assume that data "H" are transmitted to internaldata line DBW. At this time, "L" data are transmitted to internal dataline *DBW. At this time, the transistors T302 and T303 are turned on.Consequently, "H" data are transmitted to internal data line DBWathrough transistor T302 from writing circuit 303, and "L" data aretransmitted to the other internal data line *DBWa through transistorT303.

In data reading, "L" data are transmitted to both of the internal writedata lines DBW and *DBW from the input buffer circuit, and accordingly,an output from the write circuit 303 is set to a high impedance state.At this time, sense amplifier SSA is activated, and data transmitted tointernal data lines DBWa and *DBWa through a selected selecting gatecircuit 302 are amplified by the sense amplifier SSA and transmitted toan output buffer circuit through internal read data transmitting line251b'.

As shown in FIG. 73, by separately providing write data transmittingline 251a' and read data transmitting line 251b' as the internal dataline 251, design of input/output circuit layout is made easier than astructure in which writing/reading of data are carried out through acommon internal data bus.

[Refreshing Operation]

The DRAM array includes dynamic memory cells as components. Therefore,data stored therein must be refreshed periodically, or in apredetermined time period. Refreshing operation of the semiconductormemory device containing a cache will be described in the following.

Returning to FIG. 32, an external refresh designating signal REF# issupplied. Automatic refreshing (Auto-refreshing) is carried out in thesemiconductor memory device when the external refresh designating signalREF# is set to an active state of "L" at a rise of an internal clock K.

Referring to FIG. 32, circuit structure for refreshing includes an autorefresh mode detecting circuit 291 responsive to an internal refreshdesignating signal REF from a control clock buffer 250 detectingdesignation of auto-refresh; and a refresh control circuit 292responsive to a refresh request from auto refresh mode detecting circuit291 for generating various control signals and applying these signals toa counter 293 and to a multiplexer circuit 258. Counter circuit 293applies a count value stored therein to multiplexer circuit 258 as arefresh row address indicating a row to be refreshed, in response torefresh designating signal from refresh control circuit 292.

Multiplexer circuit 258 selects the refresh row address from countercircuit 293 and applies the same to DRAM row decoder 102, in response toa switch control signal MUX from refresh control circuit 292. Theinternal refresh designating signal REF is also applied to a DRAM arraydriving circuit 260. DRAM array driving circuit 260 is rendered activewhen internal refresh designating signal REF is applied and carries outoperations related to row selection in DRAM array 101.

Refresh control circuit 292 increments by one the count value in countercircuit 293 at the completion of refreshing, every time refreshdesignating signal REF is applied. Refresh control circuit 292 setsswitch control signal MUX to inactive state at the completion ofrefreshing, and in response, multiplexer circuit 258 selects an internaladdress int-Aa for internal DRAM from address buffer circuit 252 andtransmits the same to DRAM row decoder 102.

FIG. 74 functionally shows a transfer gate controlling circuit 262. Thetransfer gate controlling circuit 262 generates the signals φTDS andφTSD for controlling transfer operation of the bi-directional transfergate circuit 210 (3, BTG), in response to internal control signals E,CI, W and CH. When cache hit signal CH is active, the transfer gatecontrolling circuit 262 does not generate the transfer control signalsφTDS and φTSD. However, if array access designation (cache inhibition)signal CI is set to an active state, it successively generates controlsignals φTDS and φTSD in accordance with the state of the write enablesignal W at that time.

Transfer gate controlling circuit 262 also receives an internal refreshdesignating signal REF. The transfer gate controlling circuit 262 may beadapted to be set to the inactive state when internal refreshdesignating signal REF is applied. However, since a refresh designatingsignal REF# is applied externally, it is not necessary for transfer gatecontrolling circuit 262 to receive especially refresh designating signalREF, when generation of the array access designating signal CI isprevented by an external specification. When refreshing is being carriedout in the DRAM, SRAM array must be surely separated electrically fromthe DRAM array. If a structure is provided in which the transfer gatecontrolling circuit 262 is disabled in response to internal refreshdesignating signal REF, the SRAM array can be surely separatedelectrically from the DRAM array during refreshing operation, andexternal access to SRAM array is made possible.

Transfer gate controlling circuit 262 may have a structure in whichtransfer gate control circuit 262 is disabled when either cache hitsignal CH or refresh signal REF is made active. More preferably, a gatecircuit which sets the transfer gate control circuit 262 to a disabledstate when either cache hit signal CH or refresh designating signal RFis active should be provided. Except that time, transfer control signalsφTDS and φTSD are generated at predetermined timings in accordance withthe control signals CI and W.

FIG. 75 shows functional structure of DRAM array driving circuit 260shown in FIG. 32. DRAM array driving circuit 260 includes a rowselecting circuitry driving circuit 260a for driving circuits related torow selection of DRAM array, and a column selecting circuitry drivingcircuit 260b for driving circuits related to column selection in DRAMarray 1. Row selection circuitry driving circuit 260b generates variouscontrol signals φEQ, /φSAPE, φSANE and DWL at predetermined timings,respectively, in response to internal control signals E, CH, CI and REF.Column selecting circuitry driving circuit 260b generates a signal CDA(which corresponds to internal control signal int. *CAS) for drivingDRAM column decoder 15 at a predetermined timing in response to controlsignals E, CH, CI and REF.

Column selecting circuitry driving circuit 260b generates a columndecoder activating signal CDA at a predetermined timing when refreshdesignating signal REF is inactive and the row selecting circuitrydriving circuit 260a is made active. When refresh designating signal REFis made active, column selecting circuitry driving circuit 260b isdisabled. Consequently, column selecting operation in the DRAM isprohibited.

By this structure, when refresh designating signal REF is made active,refreshing operation in the DRAM array can be carried out independentfrom the operation of the SRAM array.

Auto refresh mode detecting circuit 291, refresh control circuit 292 andcounter circuit 293 shown in FIG. 32 operate in response to refreshdesignating signal REF, and their operations are set independent fromthe operation of a command register 270. Therefore, refreshing of DRAMarray 101 can be carried out in parallel to command mode setting of thecommand register 270. More specifically, command register 270 simplygenerates a command data CM and applies the data to a data input/outputcontrol circuit 272 and to an input/output buffer+output register block274. Data maintained therein has no influence to memory cell selectingoperation in the DRAM array 101.

Setting of data in command register 270 is completed in 1 cycle ofexternal clock signal K, as will be described in detail later withreference to a timing diagram. Refreshing operation in DRAM array needsn cycles. This is because the speed of operation of the DRAM 100 islower than that of the clock K. Therefore, in this case, in short, 1clock cycle is saved in effect. However, if the period of external clockK is made slower in accordance with the operation mode and the period issimilar to 1 memory cycle of the DRAM 100, setting of data to thecommand register 270 can be carried out in parallel to the refreshingoperation of the DRAM array 101. The change of the period of theexternal clock K enables reduction in current consumption correspondingto lowering of the speed of operation of CDRAM. More specifically, whenthe DRAM is in the standby state or when low power consumption isdesired more rather than higher speed of operation of the memory device,the speed of operation of the semiconductor memory device is lowered andthe power consumption is reduced by elongating the period of the clock.The period of the external clock K may be made longer only when accessto the DRAM only is being carried out.

By the above described structure, a CDRAM having the followingcharacteristics can be provided.

(1) The CDRAM in accordance with the present invention has a DRAM memoryarray serving as a main memory and an SRAM array serving as a cachememory integrated on one chip, and these memories are coupled to eachother by an internal bus used only for data transfer, which is differentfrom an internal common data bus. Consequently, block transfer betweenthe DRAM array and the SRAM array (cache) can be completed in 1 clockcycle. In the following description, the term "array" refers to the DRAMarray. Compared with a conventional cache memory system employing astandard DRAM and a standard SRAM, system performance can besignificantly improved.

(2) The DRAM memory array and the SRAM array can be accessed by separateand independent addresses. Therefore, various mapping methods, forexample direct mapping method, set associative method and fullassociative method can be implemented.

(3) The CDRAM operates in synchronization with an external clock K.Compared with a method in which internal clock signals are generated byusing an address change detecting circuit, delay of a cycle time derivedfrom address skew or the like can be prevented, realizing accuratecontrol.

(4) Externally applied signals (or data) such as array addresses(addresses for the DRAM) Aa0 to Aa9, cache addresses (addresses forSRAM) Ac0 to Ac11, data input/output D0 to D3 or DQ0 to DQ3, a writeenable signal W#, a cache hit signal CH#, a chip select signal E#, arefresh signal REF#, a cache inhibition signal CI# and a commandregister signal CR# are all taken at a rising edge of the external clockK.

(5) Since array addresses are taken in accordance with a multiplexingmethod, the number of pins for array addresses can be reduced,increasing packaging density of the CDRAM.

(6) Addresses of the array and of the cache are independent from eachother. At a time of a cache hit, access to the cache only is carriedout, enabling high speed cache hit accessing.

(7) Data can be read at an arbitrary timing by an output enable signalG# regardless of the timing of the external clock K, so thatasynchronous bus control can be done in the system.

(8) By using the command register 270, output specification(transparent, latch, register) and I/O structure (input/output pinseparation, masked write) can be arbitrarily designated by a user. Whena registered output method is used, output data of an address designatedin the previous cycle appears at a rising edge of the external clock K.Such data output mode is suitable for pipeline application.

In a latched output method, output data of an address designated in theprevious cycle is continuously output at the timing at which invaliddata were to be output otherwise. Therefore, invalid data is not outputat all, and valid output data only is provided. By this latched outputmode, sufficient period of time for the CPU to take output data can beprovided.

(9) Data writing operation is started at a rising edge of the externalclock K. However, writing is automatically terminated by an internaltimer or the like. Therefore, it is not necessary to set completion ofwriting operation by, for example, an external write enable signal W#,and therefore setting of timings in the system is facilitated.

(10) A refresh designating signal REF# for designating auto-refreshingcan be externally applied. Therefore, the DRAM array can beautomatically refreshed easily at a desired timing.

(11) As described above, the CDRAM of the present invention can behoused in 300 mil, TSOP package, type II having 44 pins. The TSOPpackage type II is a very thin rectangular package, which realizes asystem having high packaging density.

(12) SRAM array has a multiplicate word line arrangement in which aplurality of word lines are provided for one row of SRAM memory cells.Thus, SRAM array with high density and desired physical dimensionscorresponding to the shape of DRAM array is easily obtained to provideefficient layout of SRAM array and DRAM array on a chip, resulting inCDRAM with high density and high integration.

(13) Clamping circuits are provided for SRAM bit line pair and DRAMIOline pair.

In data transfer, the clamping circuit at a data receiving side has theclamping operation inhibited. This arhitecture provide fast datatransfer between SRAM and DRAM with less current consumption.

FIG. 76 shows, in a table, operation modes of the CDRAM of the presentinvention and states of control signals for designating respectiveoperation modes. An operation mode of CDRAM is set by a combination ofthe states of external control signals E#, CH#, CH#, CR#, W# and REF#.Referring to FIG. 76, "H" represents a high level signal potential, "L"represents a low level signal potential, and "X" represents an arbitrarystate (don't care D.C). As shown in FIG. 76, operation modes of theCDRAM includes a standby mode in which the CDRAM is set in a standbystate; an array refresh for automatically refreshing the DRAM array,data transfer between a CPU (Central Processing Unit) and a cache(SRAM); data transfer between CPU and array; data block transfer betweena cache and an array; and setting of special mode in the commandregister. Timings and combinations of the states of the signals forsetting respective operation modes will be described in detail laterwith reference to a diagram of signal waveforms. In FIG. 76, writeenable signal W# is indicated as "H/L" at data transfer between the CPUand the command register. It means that write enable signal W# is set to"H" or "L" in this operation mode, and either "H" or "L" state is usedfor designating a certain special mode.

[Command Register]

Various operation modes can be set internally by the command register.

FIGS. 77 and 78 shows the contents in the command register 270 shown inFIG. 32 and a method of selecting the contents. Command register 270includes 8 registers RR0-RR3 and WR0-WR3. Combination of write enablesignal W# and 2 bits of command addresses AR0 and AR1 is used forselecting a register. By setting the external write enable signal W# to"H" at a rising edge of external clock K, one of the registers RR0-RR3is selected. Register RR0 is selected by setting command addresses Ar0and Ar1 to "0". Register RR1 is selected by setting command address bitAr0 to "1" and command address bit Ar1 to "0". Selection of register RR0means setting of a masked write mode (this masked write mode is also adefault). Selection of the register RR1 means setting of D/Q separationmode.

When write enable signal W# is set to "L" at a rising edge of externalclock K and setting command addresses Ar0 and Ar1 both to "0", thenregister WR0 is selected. As shown in FIG. 37 or 78 this register WR0sets the output mode to transparent, latch or register mode, dependenton the combination of data at data input terminals DQ0 (D0) to DQ3 (D3)at that time. Details of the respective output modes has been describedpreviously. When register WR0 is selected, input data D2 and D3 (DQ2 andDQ3) are both set to "0". When input data D0 is set to "0" and inputdata D1 is set to an arbitrary value in this state, transparent outputmode is set. When input data D0 is set to "1" and input data D1 is setto "0", latched output mode is selected. When input data D0 and D1 areboth set to "1", registered output mode is selected. Other registers areused for arbitrary extended functions.

[Connection between CPU & DRAM]

CDRAM is employed with CPU in a data processing system. The CDRAMprovides various mapping scheme. System structure such as bus connectionis varied depending on the mapping scheme of CDRAM. Specific systemimplementation using CDRAM is described with reference FIGS. 79 and 80.

FIG. 79 is a block diagram showing a structure of a system when a cachesystem is formed by a direct mapping method using the CDRAM 600 inaccordance with the present invention. Referring to FIG. 79, the cachesystem comprises, in addition to CDRAM 600, a controller 650 forcontrolling access to the CDRAM 600, and a CPU for carrying desired dataprocessing by inputting/outputting data to and from the CDRAM 600. FIG.79 shows only an address structure output from the CPU when cache accessis required. The CPU is assumed to have 32 bits. The cache systemfurther includes an address multiplex circuit 700 for multiplexing andapplying row and column addresses to the CDRAM 600. Portions onlyrelated to cache access to the CDRAM 600 are shown as representatives.

Controller 650 includes a decoder 652 for decoding set addresses A6 toA13 from the CPU, valid bit memory 654 indicating which set is valid inresponse to an output from decoder 652, and a tag memory 656 for storingtag addresses of data stored in SRAM 200. SRAM 200 has a structure of4K×4 bits, and there are 256 tags. Therefore, tag memory 656 includes 8bits×256 structure. Valid bit memory 654 has a structure of 1 bit×256for indicating which of the 256 sets is valid. Decoder 652 decodes setaddresses A6 to A13 and makes valid one of the valid bit memory 654.

Controller 650 further includes a decoder 670 receiving addresses A22 toA31 from the CPU as a chip selecting signal for determining whether ornot a corresponding CDRAM 600 is designated, a comparator 658 which isactivated in response to an output from decoder 670, comparing a tagaddress from tag memory 656 with tag addresses A14 to A21 from CPU fordetermining a cache hit or miss, and a selector 672 in response to acache hit/miss for selecting either the tag address from tag memory 656or tag addresses A14 to A21 from CPU for applying thus selected one tothe multiplex circuit 700. At a time of a cache miss, selector 672stores tag address applied from the CPU to a corresponding position ofthe tag memory 656.

The operation will be briefly described in the following. When access tothe CDRAM 600 is requested by the CPU, addresses A2 to A31 are generatedon the data bus 620. Addresses A20 to A31 out of 30 bits of addresses oncommon data bus 620 are used as a chip select signal and applied todecoder 670 in controller 650. Decoder 670 decodes addresses A22 to A31as the chip select signal, and determines whether or not an access tothe corresponding CDRAM is requested. If it is determined that an accessto the CDRAM 600 is requested, chip select signal E# is generated fromdecoder 670 and applied to CDRAM 600. A comparator 658 is activated bythe chip select signal from decoder 670.

Decoder 652 included in controller 650 takes and decodes addresses A6 toA13 out of addresses transmitted from CPU to address bus 620 as the setaddress. Decoder 652, which has decoded 8 bits of the set address, setscorresponding bits of the valid bit memory 654 for selecting one set outof 256 sets. An address of 8 bits indicating a tag corresponding to thevalid bit of the valid bit memory 654 is read from tag memory 656 andapplied to comparator 658. Comparator 658 compares tag address from tagmemory 656 with the tag address of A14 to A21 output from CPU. When theymatch with each other, comparator 658 makes cache hit signal CH# fall to"L" and applies the same to CDRAM 600 so as to indicate a cache hit. Ifthey do not match with each other, comparator 658 generates a cache hitsignal CH# of "H" to indicate a cache miss (miss hit).

At a time of a cache hit, the following operation is carried out in theCDRAM 600. The control of operation at this time is carried out bycontrol signals from a control clock buffer 250 and by SRAM arraydriving circuit 264 (see FIG. 32). SRAM row decoder 202 selects one of256 sets in response to the set address of A6 to A13 from the CPU.Namely, one row (one in each SRAM array block, 4 rows in total) isselected. Consequently, 16 bits of SRAM cells are selected in each SRAMarray block of the SRAM 200. SRAM column decoder SCD 203 decodes theblock address of A2 to A5 from CPU, selects 1 bit out of 16 bits ofmemory cells, and connects the selected one to data input/outputterminal. FIG. 79 shows an output data Q at the time of a hit reading.

Operation at a miss hit will be described. At this time, data to whichaccess is requested by the CPU is not stored in the SRAM 200. Incontroller 650, selector 672 applies a corresponding tag address storedin tag memory 656 to multiplex circuit 700 in response to a miss hitdesignating signal from comparator 658. At this time, selector 672 hasthe 8 bits of tag address A14 to A21 applied from CPU as a new tagaddress stored at corresponding positions in tag memory 656.

In CDRAM 600, a copy back, that is, simultaneous transfer of 16 bitsfrom SRAM 200 to DRAM 100 is carried out in this cycle. Data of 16bits×4 selected by SRAM row decoder SRD 202 in accordance with the setaddress of A6 to A13 from the CPU in SRAM 200 are stored atcorresponding positions of DRAM cells of 16 bits×4 which have beenselected by row and column selecting operation in the DRAM 100 inaccordance with 8 bits of tag address output from selector 672 and inaccordance with the address A6 to A13 output from the CPU.

In the next operation cycle, CDRAM 600 selects 16 bits×4 DRAM cells inDRAM 100 in accordance with the address A6 to A21 output from the CPU,and writes the data of 16 bits×4 to corresponding 16 bits×4 memory cellsof SRAM 200 which have been selected by SRAM row decoder SRD inaccordance with address A6 to A13 from CPU. This data transfer may becarried out in accordance with the high speed transfer mode.

As described above, for the SRAM, address bits A2 to A5 are used as ablock address, address bits A6 to A13 are used as a set address, addressbits A14 to A21 are used as a tag address. For the DRAM, address bits A6to A11 are used as a column address, and address bits A12 to A21 areused as a row address. Consequently, a direct mapping method can berealized between DRAM 100 and SRAM 200.

FIG. 80 is a block diagram showing a system structure of 4 way setassociative method using the CDRAM of the present invention. CDRAM 600has the same structure as that shown in FIG. 79, which includes SRAM200, DRAM 100 and a clock control circuit 256'. Clock control circuit256' includes control clock buffer 250, SRAM array driving circuit 264and DRAM array driving circuit 260 shown in FIG. 32. For simplicity,circuit structures for controlling data input/output are omitted.

Controller 750 includes a decoder 752, a valid bit memory 754, a tagaddress memory 756, a comparator 758, a decoder 770 and a selector 772.For correspondence to 4 ways, valid bit memory 754 includes 4 memoryframes each having 1 bit×64 structure. Tag address memory 756 also has 4memory frames each having 8 bits×64 structure. Similarly, 4 comparators758 are provided for selecting one of 4 ways, that is, one comparator isprovided for each memory frame of the tag address memory 756. In 4 wayset associative method, 256 rows of SRAM 200 are divided into 4 ways,and therefore the number of sets is 64.

Addresses having the following structures are transmitted from CPU toaddress bus 620. Address of A22 to A31 is an address for selecting achip, address of A14 to A21 is a tag address, address of A12 and A13 isa way address, address of A6 to A11 is a set address, and address of A2to A5 is a block address. Address of A6 to A11 and address A12 to A21are used as a column address and a row address for the DRAM 100,respectively. Multiplex circuit 700 is provided for DRAM 100 of CDRAM600 for multiplexing the row and column addresses. The operation will bedescribed.

Address A6 to A11 from CPU is applied as a set address to decoder 752.Address of A22 to A31 is applied as a chip select address to decoder770. Decoder 752 decodes the set address of A6 to A11 and sets the validbit related to a corresponding set to valid state, in valid bit memory754. Consequently, 1 set (4 ways) is selected. Decoder 770 decodes chipselect address of A22 to A31 to determine whether or not there is anaccess request to CDRAM 600. If an access to CDRAM 600 is requested,decoder 770 sets chip select signal E# to an active state, that is, "L",and activates comparator 758. Comparator 758 reads corresponding 4 waytag addresses from tag address memory 756 referring to valid bits invalid bit memory 754, and compares the read tag addresses with theaddress of A14 to A21 from the CPU. If a matching is found, comparator758 outputs a way address of W0 and W1 indicating the way in which thematching is found, and makes cache hit signal CH# fall to "L" so as toindicate a cache hit. If there is not a match in comparator 758, cachehit signal CH# is set to "H" to indicate a miss hit.

When a cache hit occurs, way address of W0 and W1 from controller 750and address of A6 to A11 from the CPU are applied as a row address toSRAM row decoder 202, and 16 bits×4 SRAM cells are selected in SRAMarray 201. Block address A2 to A5 as a column address are decoded bySRAM column decoder 203. Out of selected 26 bits×4 SRAM cells, 1 bit×4are selected to be connected to data output terminals Q (or data inputterminals D).

In case of a miss hit, selector 772 selects one of the 4 way tag addressto select a region in which tag address is to be rewritten in accordancewith LRU (Least-Recently Used) logic. The tag address selected byselector 772 is applied as an array address to DRAM row decoder DRD inDRAM 100 through multiplex circuit 700. Selector 772 replaces the tagaddress which is to be rewritten by address of A14 to A21 applied fromthe CPU.

In CDRAM 600, the first cycle is a copy back mode. In copy back mode,way address of W0 and W1 indicating the way to be rewritten, is outputunder the control of selector 772. In SRAM 200, address of A6 to A11from CPU and way address of W0 and W1 from controller 750 are decoded,and 16 bits×4 SRAM cells are selected. In DRAM 100, 16 bits×4 DRAM cellsare selected in accordance with 8 bits of tag address output fromselector 772 and to address A6 to A13 output from the CPU. Thereafter,data are transferred from selected 16 bits×4 SRAM cells to selected 16bits×4 DRAM cells.

In the next operation cycle, 16 bits×4 DRAM cells are selected in DRAM100 in accordance with address A6 to A21 from the CPU. Data of the newlyselected 16 bits×4 DRAM cells are simultaneously transferred to 16bits×4 SRAM cells which have been selected in accordance with address A6to A11 and way address W0 and W1. The data transfer may be carried outin accordance with the high speed transfer mode.

By the above described structure, either direct mapping method or setassociative method can be realized without changing internal structureof CDRAM 600. Although not shown, full associative mapping method isalso possible. In that case, in controller 750, a tag address memory forstoring SRAM cache address and a corresponding address of the DRAM 100is necessary. Relation between signal timings in various operationcycles and state transitions in CDRAM will be described.

CDRAM operates synchronized with a clock K, to latch external controlsignal, write in data and address signal. Operation cycle of CDRAM isdetermined by combined states of external control signals at the risingedge of the clock. However, internal operation of CDRAM is advancedasynchronously with the clock K. Specific operation cycles are describedwith reference to FIGS. 81 to 104B.

As described above, control signals except output enable signal G# andaddresses Aa and Ac are latched at a rising edge of external clocksignal K. The states of respective signals are arbitrarily (D.C) exceptthat set up time and hold time are necessary before and after a risingedge of the external clock K. In accordance with the external clocksynchronizing method, it is not necessary to take cycle time marginderived from skew of address signals and the like into consideration,and the cycle time can be reduced. Thus, a CDRAM operating at high speedcan be provided.

Output enable signal G# controls the states of outputs from outputbuffer and output register included in input/output circuit 274 shown inFIG. 37. When output enable signal G# is at "H", output data is in ahigh impedance state (Hi-Z). When output enable signal G# attains toactive state, that is, "L", data is output.

[Specific Operation Cycles & Timings]

The operation modes of CDRAM are as shown in a table of FIG. 76. Therespective operation modes together with the timings thereof will bedescribed, referring to FIGS. 81 to 104B.

In the standby state, chip select signal E# and refresh designatingsignal REF# are both set to "H" at a rising edge of external clocksignal K, and remaining control signals CH#, CI#, CR# and W# are atarbitrary states. In the standby state, memory operation is not carriedout at all in CDRAM.

No. 1: Cache Hit Write Cycle

FIG. 81 shows timings of various signals in cache hit write cycle.External clock signal K has a cycle time tk. Cycle time tk includes an Hpulse width tKH at which external clock signal K is at "H", and a Lpulse width tKL at which external clock signal K is at "L". A cache hitwrite cycle is a cycle for writing data to SRAM cache. When this stateis selected, chip select signal E# is set to "L", cache hit signal CH#is set to "L", cache hit inhibition signal CI# is set to "H", commandregister signal CR# is set to "H", write enable signal W# is set to "L"and output enable signal G# is set to "H" at a rising edge of externalclock signal K.

At this state, an address for SRAM 200 is latched as valid, and accessto SRAM is carried out in accordance with the address Ac for the SRAM.At this time, an address Aa for the DRAM is arbitrary (D.C). At a risingedge of the external clock signal K, input data D is assumed valid, andvalid write data is written to SRAM cell selected by the SRAM addressAc. Since access to the cache memory SRAM is at high speed, writing iscompleted in 1 clock cycle of external clock signal K as shown in FIG.81. Namely, the time required for a cache hit writing is the clock cycletime tK.

Although output data Q changes in response to an arbitrary state (D.C.)of output enable signal G# in FIG. 81, this means that output dataappears corresponding to the "H" and "L" levels of the output enablesignal G#. FIG. 81 shows set up times and hold times of respectivecontrol signals and address signals. The set up time is necessary forsetting surely the control signal or addresses at an established stateby the time of the rising edge of external clock signal K. The hold timeis necessary for ensuring operation by holding the signal for a constanttime period from a rising edge of the external clock signal K. The setup time and the hold time will be described briefly.

Chip select signal E# includes a set up time tELS which is necessarywhen it is set to "L", a set up time tEHS which is necessary when it isset to "H", a hold time tELH necessary when it changes to "L", and ahold time tEHH which is necessary when it changes to "H".

To the cache hit signal CH#, a set up time tCHLS which is necessary whenit change to "L", a set up time tCHS which is necessary when it ischanged to "H", a hold time tCHLH which is necessary when it is changedto "L" and a hold time tCHHH which is necessary when it is changed to"H" are set.

Cache inhibition signal CI# includes set up times tCILS and tCIHS whichare necessary when it is changed to "L" and to "H", respectively, andhold times tCILH and tCIHH which are necessary when it is changed to "L"and to "H", respectively.

The command register signal CR# includes set up times tCRLS and tCRHSwhich are necessary when it is changed to "L" and to "H", respectively,and hold times tCRLH and tCRHH which are necessary when it is changed to"L" and "H", respectively.

Refresh signal RE# includes set up times tRLS and tRHS which arenecessary when it is changed to "L" and to "H", respectively, and holdtimes tRLH and tRHH which are necessary when it is changed to "L" and to"H", respectively.

Write enable signal W# includes set up times tWLS and tWHS which arenecessary when it is changed to "L" and "H", respectively, and holdtimes tWLH and tWHH which are necessary when it is changed to "L" and"H", respectively. The address Ac for SRAM includes a set up time tACSwhich is necessary for determining the state thereof as valid, and ahold time tACH which is necessary when it is valid.

The address Aa for DRAM includes a set up time tAAS which is necessaryto a rising edge of external clock signal K at which it is determinedvalid, and a hold time tAAH which is necessary after it is determined tobe valid.

As to write data D, a set up time tDS required for valid data, and ahold time tDH required for valid data are necessary.

As to output enable signal G#, time tGHD necessary from the time atwhich output is disabled to the time when data input pin is activated, adelay time tGLD which is necessary from the time at which data input pinis set to the high impedance state to the time when signal G# is changedto "L", time tGLQ which is necessary from the time when it is changed to"L" to the time when the output pin is activated, and time tGHQ which isnecessary from the time when it is changed to "H" to the time when theoutput pin is set to the high impedance state are set.

As to access time, an access time tGLA from the time when output enablesignal G# attains to "L" to an output of valid data, access time tKLAfrom the time when external clock signal K attains to "L" to an outputof valid data, an access time tKHA from the time when external clocksignal K attains to "H" to the output of valid data, an access timetKHAR from the time when external clock signal K attains to "H" inregistered output mode to the output of valid data, and an array accesstime tKHAA necessary from the time when external clock signal K attainsto "H" to the time when TRAM is accessed and valid data are output areset.

Referring to FIG. 81, after a lapse of tGHD from a rising edge of outputenable signal G#, the write data D is regarded as invalid.

The cycle time of the CDRAM of the present invention is set to 10 nS to20 nS, as an example. Array access time tKHAA is set to 70 to 80 ns.Various set up times and hold times are set to several nano seconds.

No. 2T: Cache Hit Read Cycle (Transparent Output Mode)

FIG. 82 shows timings of cache hit read cycle in the transparent outputmode. As described above, the output mode includes transparent outputmode, latched output mode and registered output mode. Designation of theoutput mode is carried out by the command register. Referring to FIG.82, when a cache hit read cycle is set, chip select signal E# and cachedesignating signal CH# are both set to "L" at a rising edge of theexternal clock signal K, and cache hit inhibition signal CI#, refreshdesignating signal REF#, command register signal CR# and write enablesignal W# are set to "H".

In this state, an address Ac for the SRAM is made valid at the risingedge of the external clock signal k, and a SRAM cell is selected inaccordance with this valid address Ac. In transparent output mode, dataof the SRAM cell designated by the valid address Ac is output in thisclock cycle. In transparent output mode, valid output data Q is outputafter a lapse of tKHA from the rising edge of the external clock K orafter a lapse of time tGLA from a falling edge of output enable signalG#, which ever is later.

When output enable signal G# falls to "L" before the time tKHA, invaliddata is continuously output until the time tKHA has lapsed. In the cachehit read cycle, write data is set to high impedance state (Hi-Z), andthe address Aa from the DRAM may be set to any state, since it is notused.

No. 2L: Cache Hit Read Cycle (Latch Output Mode)

FIG. 83 shows timings in cache hit read cycle of latched output mode.The difference between latched output mode and transparent output modeis that when output enable signal G# falls to "L" before the access timetKHA, data of the SRAM cell which has been selected in the previouscycle (Pre.Valid) is output at first. Other signal timings are the sameas those in transparent output mode shown in FIG. 82. In the latchoutput mode, invalid data (INV) is not output. Valid data only areoutput.

No. 2R: Cache Hit Read Cycle (Register Output Mode)

FIG. 84 is a timing diagram of the cache hit read cycle in registeredoutput mode. Timings of external control signals in the cache hit readcycle of the registered output mode are the same as those in thetransparent output mode and in the latched output mode shown in FIGS. 82and 83. In the registered output mode, valid data of the previous cycle(Pre.Valid) is output after the lapse of tKHAR from the rising edge ofexternal clock signal K or after a lapse of time tGLA from a fallingedge of output enable signal G#, which is later. In registered outputmode, invalid data is not output. Register output mode is suitable forpipeline operation.

Switching of the above described output modes is realized by controllingthe operation of an output register included in input/output circuit 274shown in FIGS. 32 and 37 (particularly see FIG. 37).

No. 3: Copy Back Cycle

FIG. 85 shows timings of various signals in copy back cycle. The copyback cycle is a cycle for transferring data from cache (SRAM) to array(DRAM), and it is carried out as a first cycle at a time of a miss hit.In the copy back cycle, chip select signal E# and write enable signal W#are both set to "L", and cache hit signal CH#, cache inhibition signalCI#, refresh designating signal REF#, command register signal CR# andoutput enable signal G# are set to "H" at a rising edge of externalclock signal K. In the copy back cycle, an array address Aa must beinput to DRAM for selecting the memory cells. A row address (Row) andthe column address (Col) are multiplexed and applied as the arrayaddress Aa. An array row address is latched at a first rising edge ofexternal clock signal K, and an array column address is latched at asecond rising edge of external clock signal K. At the second rising edgeof external clock signal K, cache hit designating signal CH#, cacheinhibition signal CI#, write enable signal W# and cache address (addressto SRAM) Ac may be at arbitrary states.

Write enable signal W# has been set to "L" at the first rising edge ofexternal clock signal K, and external input data D changes from highimpedance state to an arbitrary state. External output data Q is set tohigh impedance state, since output enable signal G# is at "H".

No. 4: Block Transfer Cycle

In block transfer cycle shown in FIG. 86, a data block is transferred atone time from the array to the cache (SRAM) before, after orsimultaneously with a copy back operation. Timing conditions which arethe same as in the copy back cycle shown in FIG. 85 are satisfied in theblock transfer cycle, except that write enable signal W# is set to "H"at a first rising edge of the external clock signal K.

More specifically, when write enable signal W# is set to "L" at thefirst rising edge of external clock signal K at a cache miss (miss hit),the copy cycle is started. If write enable signal W# is set to "H",block transfer cycle from the array to the cache is set.

Whether a high speed copy back is to be carried out or normal copy backand block transfer is to be carried out, or whether write throughoperation is to be carried out is determined by setting of command datato the command registers.

No. 5: Array Write Cycle

The array write cycle shown in FIG. 87 is a cycle for setting a mode inwhich CPU directly accesses to the array for writing data. A DRAM cellin the array is selected by array address Aa. At this time, data may bewritten through access switching circuit 310 of bi-directional transfergate circuit 305 as shown in FIG. 33. Alternatively, data may be writtenthrough SRAM bit line pair SBL, the bi-directional transfer gate BTG andglobal I/O line pair GIO as shown in FIGS. 49 and 57, without providingaccess switching circuit 310. If the structure is adapted to write datathrough SRAM bit line pair SBL in SRAM array, lower bits of arrayaddress Aa may be applied to column decoder SCD of SRAM as a blockaddress. A column selecting signal may be applied from DRAM columndecoder to SRAM selecting gate.

Array write cycle is designated by setting chip select signal E#, cacheinhibition signal CI# and write enable signal W# to "L" and by settingrefresh designating signal REF# and output enable signal G# to "H" atthe first rising edge of external clock signal K, as shown in FIG. 87.Cache designating signal CH# may be at an arbitrary state. In arraywrite cycle, array address Aa is latched as a row address (row) at thefirst rising edge of external clock signal K, and array address Aa islatched as a column address (Col) at the second rising edge of externalclock signal K. Since the cache is not accessed at this time, address Acfor the cache may be at an arbitrary state. External write data D islatched at the first rising edge of external clock signal K. Externaloutput data Q is set to high impedance state.

In the cache system shown in FIGS. 79 and 80, only 16 bits of an addressare applied to DRAM 100, and column selecting operation in blocks iscarried out in accordance with the block address in SRAM. FIGS. 79 and80 show a structure for a cache system and those figures do not show thestructure of the array access. However, the structure may use 4 bits ofa block address as column selecting address for DRAM 100, when cacheinhibition signal CI# attains to "L" at array accessing.

No. 6: Array Read Cycle

Array read cycle shown in FIG. 88 is a cycle for setting a mode in whichCPU directly accesses to array for reading data. Array read cycle isdesignated by setting chip select signal E# and cache inhibition signalCI# to "L" and by setting refresh designating signal REF#, commandregister signal CRY, write enable signal W# and output enable signal G#to "H" at the first rising edge of external clock signal K. At thesecond rising edge of external clock signal K, chip select signal E#,refresh designating signal REF# and command register signal CR# are setto "H", and cache inhibition signal CI# and write enable signal W# maybe at an arbitrary state. The cache hit designating signal CH# may be atan arbitrary state in array read cycle. Output enable signal G# ismaintained at "H". Array address Aa is latched as a row address at thefirst rising edge of external clock signal K, and array address Aa islatched as a column address at the second rising edge of the externalclock signal K. External input data D may be at an arbitrary state, andexternal output data Q is set to high impedance state.

Array access cycles (array write cycle and array read cycle) are set bysetting cache signal CI# to "L" at the first rising edge of the externalclock signal K. The array access cycles are cycles for setting modes inwhich CPU directly accesses the array. Data reading/writing are notactually carried out in the array write cycle and array read cycle.

In operations such as copy back operation, block transfer operation andarray access operation which require reading/writing of data in thearray, selection of a word line in the DRAM array, detection andamplification of data in the selected cells by sense amplifiers, restoreoperation of data, and RAS precharge are necessary. Therefore, theseoperations requiring reading/writing of data in the array takes severalclock cycles. When we represent the cycle time of the DRAM by tA and thecycle time of the external clock signal K as tK, external clock cyclesof m=ta/tK is necessary for the array access. m cycles correspond to await time for the CPU. Timings when the CPU is kept in a waiting statein reading/writing data while memory cells are selected in the arraywill be described.

No. 7: Array Active Cycle

In array active cycle shown in FIG. 89, row selecting operation, columnselecting operation and data writing/reading are carried out inaccordance with the applied array address Aa. In array active cycle,chip select signal E#, refresh designating signal REF# and commandregister signal CR# are set to "H" at a rising edge of external clockssignal K, and output enable signal G# is fixed at "H" for this cycle.Cache hit signal CH#, cache inhibition signal CI# and write enablesignal W# may be at an arbitrary state. External input data D may be atan arbitrary state and external output data Q is set at high impedancestate in the array active cycle.

No. 7QT: Array Active Cycle Accompanied with Transparent Output Mode

Control signals E#, CH#, CI#, REF#, CR# and W# are set in the samemanner as in the array active cycle shown in FIG. 89 for designating thearray active cycle in the transparent output mode shown in FIG. 90. Inthe array active cycle in transparent output mode, when the outputenable signal G# is set to "L", an output buffer is activated and validdata are output. In array active cycle of the transparent output mode,data of the DRAM cells corresponding to the array address Aa set inarray read cycle shown in FIG. 88 are output.

No. 7QL: Array Active Cycle in Latched Output Mode

Timings of control signals in array active cycle of the latched outputmode shown in FIG. 91 are the same as those shown in FIG. 89. Data(latched in an output register) read in the previous access cycle(either a cache access cycle or array access cycle) is output at first,then data read in the current array access cycle is output.

No. 7QR: Array Active Cycle in Registered Output Mode

States of control signals in the array active cycle in registered outputmode shown in FIG. 92 are the same as those shown in FIGS. 90 and 91. Inthe array active cycle of the registered output mode, when output enablesignal G# which has been maintained at "H" is set to "L", external writedata D is set to the high impedance state, and data read in the previousaccess cycle is output in the current cycle. In the registered outputmode array access cycle, when output enable signal G# falls from "H" to"L" at the next clock cycle, data read in the current array access cycleis output.

By combining cycles shown in FIGS. 88 to 92, output data Q in accordancewith an external address can be provided from the array.

FIG. 93 shows the cycles executed when data are read from the array intransparent output mode. In FIG. 93, numerals in circles at the upperportion of the timing diagram correspond to numbers allotted to theabove description of respective cycles.

In array reading operation in the transparent output mode, the arrayread cycle (No. 6) shown in FIG. 88 is executed. In this cycle No. 6,the array address Aa is successively taken as the row address and thecolumn address at the rising edges of the external clock signal K.Thereafter, the array active cycle shown in FIG. 89 is carried out for aprescribed number of times, for selecting rows and columns in the DRAMarray. Finally, the cycle No. 7 shown in FIG. 90 is executed, and bymaking output enable signal G# fall to "L", invalid data is output, andthen valid data is output. In this case, access time tKHAA isapproximately the same as the access time in a normal DRAM.

FIG. 94 shows the cycles carried out when data are read from the arrayin the latched output mode. In the array reading operation in thelatched output mode also, at first the array read cycle (No. 6) shown inFIG. 88 is executed, as in the array reading operation in thetransparent output mode shown in FIG. 93, and mode for reading data fromthe array is set. After the array address Aa has been latched by thisarray read cycle (cycle No. 6), array active cycle shown in FIG. 89(cycle No. 7) is carried out for a predetermined number of times. Afterthe array active cycle (cycle No. 7), an array active cycle in thelatched output mode (cycle No. 7QL) shown in FIG. 90 is executed. Whenoutput enable signal G# which has been set at "H" falls to "L" in thiscycle No. 7QL, data read by the previous access is output, and then dataof the memory cell to which access is requested in the present arrayread cycle is output. The access time tKHAA at this time corresponds tothe time required from the first rising edge of the external clocksignal K to the output of memory cell data (valid) to which access isrequested in the present array access cycle.

FIG. 95 shows cycles carried out when data are read from the array inregistered output mode. Referring to FIG. 95, first the cycle No. 6 isexecuted and array read mode is set. At a rising edge of external clocksignal K, the array address Aa is time divisionally latched as the rowaddress and the column address. Thereafter, the array active cycle ofcycle No. 7 is carried out for a predetermined number of times, and thenthe array active cycle of cycle No. 7QR is executed. In this cycle No.7QR, after a time lapse of tQHA or tGLA which is later after the rise ofthe external clock signal K and after the fall of the output enablesignal G# to "L", data read in the previous cycle is output as theoutput data Q. The access time tKHAA is the time from the first risingedge of the external clock signal K to the output of valid data in cycleNo. 6.

The DRAM cells must be refreshed periodically. Setting of the refreshoperation is done by an external refresh designating signal REF#. In therefreshing operation, a refresh address is generated from a refreshaddress counter (see counter circuit 293 of FIG. 32) in response torefresh designating signal REF# in the CDRAM, and DRAM cells areautomatically refreshed in accordance with the refresh address. DRAMshaving such auto-refreshing function have been known in the field ofDRAMs. Timings of signals for refreshing will be described.

No. 8: Refresh Cycle

FIG. 96 shows signal timings of the refresh cycle. As shown in FIG. 86,refresh mode of the DRAM is set by setting chip select signal E# andrefresh designating signal REF# to "H" and "L", respectively, at arising edge of external clock signal K as shown in FIG. 96. When chipselect signal E# is set to "H" and refresh designating signal REF# isset to "H" at a rising edge of the external clock signal K, refreshingof the DRAM is stopped. In the refresh cycle, other control signals CH#,CI#, CR# and W# may be at arbitrary states, and the output enable signalG# is set to "H". Therefore, the cache address Ac and array address Aamay be at arbitrary states. External input data D also may be set at anarbitrary state. External output data Q is set to a high impedancestate.

Refreshing operation is effected only to the DRAM. Refreshing is notnecessary in the SRAM. Therefore, cache (SRAM) can be accessed duringthe refreshing operation.

Timings where refreshing operation and access to the cache aresimultaneously carried out will be described in the following.

No. 8W: Refresh Cycle with Cache Hit Writing

In cycle No. 8W, in parallel to refreshing of the DRAM, writing of datato a corresponding SRAM cell is carried out when a cache hit occurs.Setting of the refresh cycle with the cache hit writing is set bysetting chip select signal E#, cache hit signal CH#, refresh designatingsignal REF# and write enable signal W# to "L" and by setting cacheinhibition signal CI# and output enable signal G# to "H" at a risingedge of external clock signal K as shown in FIG. 97. Thus a cache hitwrite cycle is set and refresh cycle is set.

In the cache (SRAM), external write data D is taken and then written toa corresponding SRAM cell at a rising edge of external clock signal K,in response to active states of the cache hit designating signal CH# andwrite enable signal W#. In the DRAM, an internal refresh address counteris started by the refresh designating signal REF#, and refreshingoperation is carried out in accordance with a refresh address from thecounter.

When refresh designating signal REF# is set to "H" at a rising edge ofexternal clock signal K, the cache hit write cycle (cycle No. 1) shownin FIG. 81 only is carried out, and refreshing operation of the DRAM isstopped.

No. 8RT: Refresh Cycle with Cache Hit Reading in Transparent Output Mode

In cycle No. 8RT, cache hit reading is carried out in accordance withthe transparent output mode, and DRAM is automatically refreshed. Thecycle No. 8 is set by setting the chip select signal E#, cache hitsignal CH# and refresh designating signal REF# to "L" at a rising edgeof external clock signal K, and by setting cache inhibition signal CI#,command register signal CR# and write enable signal W# to "H" as shownin FIG. 98. In SRAM cache, cache address Ac at a rising edge of externalclock signal K is taken and a corresponding SRAM cell is selected inresponse to the designation of cache hit reading. When output enablesignal G# falls to "L", valid output data Q is output after a lapse of apredetermined time period.

In the DRAM, auto-refreshing is carried out in response to refreshdesignating signal REF#. When refresh designating signal REF# is set to"H" at a rising edge of external clock signal K in refresh cycle withcache hit reading, automatic refreshing carried out in response torefresh designating signal REF# is stopped. Therefore, in this case,cache hit read cycle in the transparent output mode which is the same asthe cycle No. 2T is carried out.

No. 8RL: Refresh Cycle with Cache Hit Read in Latch Output Mode

In cycle No. 8RL shown in FIG. 89, cache hit reading in latched outputmode is carried out together with auto-refreshing of the DRAM. Timingconditions of various control signals are the same as those shown inFIGS. 87 and 88. In the latched output mode, when a cache hit occurs,output enable signal G# falls to "L", then data accessed in the previouscycle is output, and successively data accessed in the present cycle isoutput.

No. 8RR: Refresh Cycle with Cache Hit Read Cycle in Register Output Mode

In cycle No. 8RR shown in FIG. 100, data reading is carried out inaccordance with the cache hit read cycle in the registered output mode,and the DRAM is automatically refreshed. Timing conditions of variouscontrol signals are the same as those shown in FIGS. 97 and 98, and hitreading and auto-refreshing are carried out. In this cycle No. 8RR, whenoutput enable signal G# falls to "L", output data selected in theprevious cycle is output. Thereafter, output enable signal G# is onceraised to "H", and thereafter output enable signal G# is set to "L", inthe next clock cycle, and then data of the SRAM cell selected in thepresent cycle is output.

The transparentoutput mode, latched output mode, registered output mode,masked write mode and D/Q separation mode of the CDRAM can be realizedby setting commands for setting desired special function in the commandregister. Operation cycle for setting commands in the command registerwill be described in the following.

No. 9: Command Register Set Cycle

FIG. 101 shows timings of various signals in command register set cycle(cycle No. 9). The command registers set cycle is realized by settingchip select signal cache inhibition signal CI#, command register signalCR# and write enable signal W# to "L" at a rising edge of external clocksignal K. At this time, any one of four registers WR0 to WR3 of thecommand register is selected as shown in FIG. 77. Command register WR0is selected in setting the output mode, and the kind of the output modeis selected dependent on the combination of the input data D at thattime. Therefore, at a rising edge of the external clock signal K, acommand address Ar and an external write data D are regarded as validand latched. When 2 bits Ar0 and Ar1 of the command address AR are both0 ("L"), the command register WR0 is selected. When upper 2 bits D2(DQ2) and D3 (DQ3) of 4 bits of external write data D are "0" ("L") andthe least significant bit D0 (DQ0) is "0" of 4 bits of external writedata D, the transparent output mode is set.

The latched output mode is selected by setting external write data D0and D1 to "1" ("H") and "0", respectively and by setting remaining 2bits of external write data D2 and D3 to "0" at a rising edge ofexternal clock signal K. The registered output mode is selected bysetting command address Ar0 and Ar1 to "0", setting external write dataD0 and D1 (DQ0 and DQ1) both to "1" and by setting external write dataD2 and D3 (DQ2 and DQ3) both "0" at a rising edge of external clocksignal K.

In the structure of the command registers shown in FIG. 77, 8 registersare provided, enabling setting of 8 different special modes. The commandregister RR0 for setting the masked write mode, and the register RR1 forsetting D/Q separation mode are selected by setting write enable signalW# to "H" at the timing shown in FIG. 91. Dependent on the value of thecommand address Ar at this time, a desired mode can be selected.

FIGS. 102A and 102B show state transition of the CDRAM at a time of acache miss (miss hit). FIG. 102A shows a flow of state transition, andFIG. 102B shows state transition between respective cycles. In FIG. 102the cycles are denoted by cycle numbers.

Referring to FIG. 102A, when a cache miss occurs, a copy back cycle(cycle No. 3) shown in FIG. 85 is carried out at first. Consequently,data transfer mode from the SRAM to DRAM is set. Thereafter, arrayaccess cycle (cycle No. 7) shown in FIG. 89 is repeated for n(n=(ta/tk)=1) times. The character ta represents cycle time of the DRAM,and tk represents cycle time of the external clock K. By repeating cycleNo. 7 for n times, collective transfer of data blocks from SRAM to DRAMis completed. Thereafter, block transfer cycle (cycle No. 4) shown inFIG. 86 is carried out. Consequently, data transfer mode from DRAM toSRAM is set. By repeating cycle No. 7 for n times successive to thecycle No. 4, transfer of data blocks from DRAM to SRAM is carried out.Thereafter, the DRAM is ready for receiving next access. This state isreferred to as a block transfer mode. From this time on, the CPU canaccess to SRAM or DRAM.

When array active cycle (cycle No. 7) is repeated for n'(n'=(ta/2.tK)-1) times successive to the cycle No. 4, restore operationto the memory cell and RS precharging are not yet completed in the DRAM,and therefore it cannot be accessed. However, in the SRAM, block datahas been already transferred from the DRAM in this state, restore is notnecessary, and data on the SRAM bit line pair has been established.Therefore, the CPU can access to the SRAM at this state. This state isreferred to as a cache fill state. In the cache fill state, the CPU canaccess only to the SRAM. Either the cache hit write cycle (cycle No. 1)shown in FIG. 81 or cache hit read cycle (cycle No. 2) shown in FIGS. 82to 84 is carried out after cache fill. The cache hit read cycle (cycleNo. 2) may be carried out in transparent output mode, latched outputmode or registered output mode. Hit writing can be successively carriedout at every clock cycle, and hit read cycle can be successively carriedout at every clock cycle. The operation may be switched from the hitread cycle to the hit write cycle. Data transfer may be carried out inaccordance with the high speed transfer mode (fast copy back) in which"copy back" and "block transfer" are carried out parallel to each other.

FIGS. 103A and 103B shows state transition at a time of array accessing.FIG. 103A (A) shows a flow of state transition in array access, and FIG.103B (B) shows state transition between respective cycles. Array accessincludes array writing to write data to the array, and array read forreading data from the array. In array writing, array write cycle (cycleNo. 5) shown in FIG. 83 is carried out. Successive to the cycle No. 5,the array active cycle of cycle No. 7 is repeated for n times to writedata to the DRAM array.

In array reading, the array read cycle (cycle No. 6) shown in FIG. 88 iscarried out, and access to the DRAM is enabled. After the array readcycle (cycle No. 6), the array active cycle shown in FIG. 89 (cycle No.7) is repeated for n' times. At this state, data cannot be read fromDRAM. Subsequent to the cycle No. 7, the array active cycle for dataoutput (cycle No. 7Q) shown in FIGS. 90 to 92 is repeated for n'+1times. The cycle No. 7Q may be the array active cycle for transparentoutput, array active cycle with latch output, or array active cycle withregistered output.

By setting output enable signal G3 to "L" at the last cycle of the cycleNo. 7Q, data can be read from the array. The cycle times of the arraywriting and array reading seem to be different from each other. However,n=n'+1, and therefore reading and writing of data from and to the arraycan be carried out in the same clock cycles. After the array writingoperation or array reading operation, array writing or array reading canbe successively carried out.

FIGS. 104A and 104B show the state transition at a time of refreshing.FIG. 104A is a flow of state transition of the refreshing operation, andFIG. 89B shows state transition between respective cycles at the time ofrefreshing.

In normal refreshing in which auto-refreshing of DRAM only is carriedout and access to SRAM is not carried out, first the refresh cycle(cycle No. 8) shown in FIG. 96 is carried out. Thereafter, the arrayactive cycle (cycle No. 7) shown in FIG. 84 is repeated for n times.Consequently, one auto-refreshing operation in accordance with therefresh address from the refresh counter contained in the CDRAM iscompleted.

In refreshing with hit writing, the refresh cycle with cache hit writingshown in FIG. 97 (cycle No. 8W) is carried out at first. Then,auto-refreshing of the DRAM is carried out for the n successive clockcycles. During this period, the cache hit write cycle shown in FIG. 81can be executed by the CPU for n times.

In refresh cycle with hit reading, the refresh cycle with cache hitreading shown in FIGS. 98 to 100 (cycle No. 8R) is carried out.Consequently, auto-refreshing of the DRAM is started, andauto-refreshing is carried out for n clock cycles in the DRAM. CPU canexecute hit reading during the n clock cycles. The output mode of thecycle No. 8R may be transparent output mode, latched output mode orregistered output mode.

[Second Embodiment]

Basic constructions, arrangements and operations of CDRAM of the presentinvention have been described. Various modifications and additionalfunctions can be considered, which will be described as a secondembodiment in the following.

In the second embodiment, control signal CI# (cache access inhibitingsignal) and a command set/burst enable signal CR#/BE# applied to the pinnumber 4 are defined as control signals CC1 and CC2. These signals havethe same function as in the first embodiment described above, and onlythe names of the signals are changed.

[Low Power and High Speed Operations Modes]

It is desirable to change the clock frequency according to the situationof accessing to CDRAM in terms of power consumption. For example, whenonly DRAM in CDRAM is successively accessed, no fast clock is needed asits operating speed is slow. So, a low clock is preferable in suchsituation in terms of low power consumption. If SRAM cache issuccessively accessed, a fast clock should be applied in terms of fastoperationability. CDRAM should operate as fast as possible with leastpower consumption regardless of clock frequency. In order to implementsuch operating characteristics, DRAM address strobing timing is variedaccording to the clock frequency. More specifically, CDRAM is adapted toinclude two operation modes, i.e. low power consumption mode in whichDRAM row address is latched at a leading edge of the clock K while DRAMcolumn address is latched at the following trailing edge of the clock K,and high speed mode in which DRAM row address is latched at a leadingedge of the clock K while DRAM column address is latched at anotherleading edge of the clock K. In the following, structure forimplementing such changing of address strobe timing is described withreference to FIGS. 105 through 118.

FIG. 105 is a block diagram showing functionally the whole structure ofthe CDRAM in accordance with the second embodiment. In the CDRAM shownin FIG. 105, an address generating circuit 360 which takes externaladdress signals Ac and Aa and generates internal addresses int-Ac andint-Aa in accordance with internal chip enable signal E, internal cachehit designating signal /CH and an internal clock signal int-K from clockbuffer 254 is provided in place of address buffer 260 shown in FIG. 32.By adjusting timings of taking addresses Ac and Aa in address generatingcircuit 360, the CDRAM 5000 can be set to either one of low powerconsumption mode and high speed operation mode.

A row address signal and a column address signal are externally appliedtime divisionally to provide the DRAM internal address signal int-Aaapplied to DRAM row decoder 102 and DRAM column decoder 103. Byadjusting timings for taking these address signals, the speed ofoperation of DRAM can be adjusted. Address generating circuit 360generates an internal row address signal and an internal column addresssignal while adjusting the timing for taking the external DRAM addresssignal Aa in accordance with an internal control signal K (int-K) andinternal control signals E and /CH.

FIG. 106 is a diagram of signal waveforms showing the operation ofcircuitry related to the portion generating the internal address signalint-Aa for the DRAM of this address generating circuit 360. Theoperation of address generating circuit 360 will be described withreference to FIG. 106.

An operation mode in which high speed operation is carried out with lowpower consumption (hereinafter referred to as a low power consumptionmode) is set by setting, at time T1, the internal control signals E andCH to "H" and "L", respectively, at a rising edge of the clock signal K.At this time, address generating circuit 360 takes external addresssignal Aa as an internal row address signal int-Aar in response to therising edge of the clock signal K. Then, it takes external addresssignal Aa in response to a falling edge of the clock K and generates aninternal column address signal int-Aac. The details of this operation isas follows.

At time T1, the external address signal Aa has been already applied toaddress generating circuit 360 at the rising edge of the external clocksignal K. At this time, in accordance with the combination of the statesof the signals E and CH, an internal row address strobe signal /RAS fortaking a row address signal is generated and set to an active state of"L". Since internal row address strobe signal /RAS is a signal of active"L", address generating circuit 360 latches external address signal Aaand thereafter continuously generates internal row address signalint.Aar and applies the same to DRAM row decoder 102 (time T2).

When internal row address strobe signal /RAS is at "L" at a falling edgeof the external clock signal K at time T3, internal column addressstrobe signals CAL and /CAL are generated. In response, addressgenerating circuit 360 takes and latches the external address signal Aaas an internal column address signal (time T4), and applies the same toDRAM column decoder 103.

The scheme shown in FIG. 106 which DRAM row address signal int.Aar andDRAM column address signal int.Aac are taken by a single pulse of clocksignal K enables faster operation of the DRAM compared with thestructure of a common clock synchronized type semiconductor memorydevice such as shown in FIG. 107 in which operation is effected only atthe rising edge of the external clock signal.

Namely, as shown in FIG. 107, in the low power consumption mode, the rowaddress signal and the column address signal for the DRAM are taken attime TA, at which the operation for the DRAM is started.

If all operations are determined at the same timing (rising edge) of theclock signal K as in the conventional clock synchronized typesemiconductor memory device, the column address signal for the DRAM istaken at the rising edge of the next clock signal K (time TB), and fromthis point of taking the column address signal, the DRAM starts itsoperation. Therefore, even when power consumption is given priority thanthe speed of operation of the CDRAM and the period of the clock signal Kis made longer or the clock signal K is generated intermittently inorder to reduce power consumption of the CDRAM, the start point ofoperation of the DRAM can be made earlier by the time period (TB-TA)between TB and TA, compared with the structure of the conventional clocksynchronized type semiconductor memory device. Namely, a clocksynchronized type semiconductor memory device which can be operated athigh speed even in the low power consumption mode can be provided.

As shown in FIG. 105, internal operations of CDRAM are all controlled bythe external control signals. Internal row address strobe signal /RASand internal column address strobe signals CAL and /CAL shown in FIG.106 are control signals which simply determines the timing of takingDRAM addresses in address generating circuit 360.

Assume that the external clock signal K is generated intermittently inorder to further reduce power consumption, while period of the externalclock signal K is made longer so as to meet the demand of low powerconsumption. In this case also, by resetting the taking operation ofaddress generating circuit 360 by utilizing internal row address strobesignal /RAS, a CDRAM which can minimize an influence of possible noisegenerated in such intermittent operation can be provided. Here, theintermittent operation mode corresponds to a mode in which period of theclock signal K is made longer temporarily, or a mode in which period ofthe external clock signal K is variable. A margin for noise pulsesgenerated when the period of the external clock signal is long will bedescribed.

FIG. 108 is a diagram for comparison between the conventional operationmode and the low power consumption mode. In the low power consumptionmode, if a noise pulse NZ is generated in the external clock signal K,external address signal Aa is taken in the CDRAM at time TC, thenexternal address signal Aa is taken as an internal column address signalat time TD, and the DRAM starts its operation from time TD. However, ifthe structure is adapted to reset address generating circuit 360 afterthe lapse of a prescribed time period, the operation of the DRAMterminates automatically at time TE, and malfunction caused by the noisepulse NZ can be prevented. More specifically, when external clock signalK rises at time TEa, the operation of the DRAM has been alreadycompleted and it is returned to the precharge state. Accordingly,operations in accordance with the combinations of the states of variouscontrol signals at the rising edge of the external clock signal K can becarried out, and therefore a CDRAM having sufficient margin for themalfunction of the noise pulse NZ can be provided.

When the row address signal and the column address signal are to betaken only at the rising edge of the external clock signal K as in thenormal mode, and if the row address signal is erroneously taken inresponse to a rising edge of the noise pulse NZ at time TC, the CDRAM iskept in a waiting state for the input of the column address signal untilthe next rising point TEa of the external clock signal K. At this time,the CDRAM takes address signal Aa, at time TEa when the accurateexternal clock signal K rises, as a column address signal and starts itsoperation. Therefore, when an accurate external clock signal K isapplied, an erroneous operation is effected. Namely, because of thelonger period of the external clock signal K to reduce powerconsumption, margin for the noise is lost in the conventional operatingmode.

As described above, by resetting the DRAM after the lapse of apredetermined time period (for example, time required till completion ofthe sensing operation in the DRAM array) from taking of the DRAM columnaddress signal in address generating circuit 360, sufficient margin forthe noise can be provided even if the external clock signal K is appliedintermittently.

FIG. 109 shows an example of a specific structure of address generatingcircuit 360 shown in FIG. 105. Referring to FIG. 109, address generatingcircuit 360 includes a row address strobe signal generating circuit 2601responsive to control signals E and CH and to external clock signal Kfor generating an internal row address strobe signal /RAS; a columnaddress strobe signal generating circuit 2602 responsive to internal rowaddress strobe signal /RAS from row address strobe signal generatingcircuit 2601 and to clock signal K for generating internal columnaddress strobe signals CAL, /CAL; a row address latch 2603 responsive tointernal row address strobe signal /RAS for taking external addresssignal Aa to generate an internal row address signal; a column addresslatch 2604 responsive to internal row address strobe signal /RAS andinternal column address strobe signals CAL and /CAL for taking externaladdress signal Aa to generate an internal column address signal; and areset signal generating circuit 2605 responsive to internal row addressstrobe signal /RAS for generating a reset signal after a lapse of apredetermined time period (for example, period of active state of theDRAM) to apply the same to row address strobe signal generating circuit2601. Here, external clock signal K and internal clock signal int-K aresubstantially the same signal, and in the following, internal clocksignal is simply referred to as K.

The row address strobe signal generating circuit 2601 generates internalrow address strobe signal /RAS when control signal E is at "H" andcontrol signal CH is at "L" at a rising edge of (internal) clock signalK. Column address strobe signal generating circuit 2602 generatesinternal column address strobe signals CAL, /CAL in response to afalling edge Of clock signal K. Column address strobe signal generatingcircuit 2602 is reset when internal row address strobe signal /RAS risesto inactive "H".

Row address latch 2603 is set to a latch state when internal row addressstrobe signal /RAS attains "L" and outputs continuously the latchedsignal as internal row address signal regardless of the state ofexternal address signal Aa.

Column address latch 2604 takes external address Aa in response tointernal row address strobe signal /RAS, and outputs applied addresssignal continuously as internal column address signal in response tocolumn address strobe signals CAL, /CAL. The address generating circuitshown in FIG. 109 is related to DRAM addresses. At a time of cache hitin which SRAM array is accessed, the row address signal and the columnaddress signal are simultaneously applied to SRAM address generatingcircuit (not shown). Therefore, the row address signal and the columnaddress signal for SRAM are taken at the same timing of the externalclock signal. The operation of the address signal generating circuitshown in FIG. 109 is the same as that described with reference to thediagram of signal waveforms of FIG. 106, and therefore descriptionthereof is not repeated. Specific structure of respective circuits inFIG. 109 will be described.

FIG. 110 shows a specific structure of row address strobe signalgenerating circuit 2601 shown in FIG. 109. Referring to FIG. 100, rowaddress strobe signal generating circuit 2601 includes an AND circuit2610 receiving the clock signal K, control signal E and control signal/CH (inverted signal of CH); and an OR circuit 2611 receiving at oneinput, the output from AND circuit 2610, and receiving at the otherinput, a Q output of a flipflop (FF) 2612. Flipflop 2612 includes a setinput S receiving an output from OR circuit 2611, a reset input Rreceiving a reset signal RS from reset signal generating circuit 2605shown in FIG. 109, a Q output and /Q output. Q output and /Q outputprovide signals complementary to each other.

Internal row address strobe signal /RAS is generated from /Q output fromflipflop 2612. Generally, flipflop 2612 has a circuit structureincluding two NOR circuits cross coupled to each other. The flipflop2612 is set when "H" signal is applied to set input S, and outputs asignal at "L" from /Q output. When a signal at "H" is applied to resetinput R, it is reset and signal output from /Q attains "H". Operation ofrow address strobe signal generating circuit 2601 shown in FIG. 110 willbe described with reference to the diagram of waveforms of FIG. 106.

When control signal E is at "H" and control signal C is at "L" whenclock signal K rises to "H", then the output from AND circuit 2610attains to "H". Consequently, the output from OR circuit 2611 rises to"H" and flipflop 2612 is set. Then, internal row address strobe signal/RAS provided as an output from /Q output of flipflop 2612 falls to "L".At this time, Q output of flipflop 2612 attains "H" and output from ORcircuit 2611 attains "H". After a lapse of a predetermined time periodfrom the generation of internal row address strobe signal /RAS, a resetsignal is generated from reset signal generating circuit 2605 (see FIG.109), flipflop 2612 is reset and row address strobe signal /RAS rises to"H". Therefore, the row address generating circuit 360 is ready toreceive the next address.

When a reset signal of "H" is applied while "H" signal being applied toset input S of flipflop 2612 having NOR gates cross coupled to eachother, Q output and /Q output may both attain "L". At this time, since Qoutput of flipflop 2612 is applied to one input of OR circuit 2611, theoutput of OR circuit 2611 attains "L". If reset signal RS has anappropriate pulse width, flipflop 2612 is kept at a stable reset state.In order to ensure operation of flipflop 2612 at this time, a one shotpulse signal may be generated when Q output of flipflop 2612 attains to"H" to apply the one shot pulse signal to OR circuit 2611 in place of Qoutput of flipflop 2612. Alternatively, a circuit generating a one shotpulse having an appropriate pulse width in response to an output fromAND circuit 2610 may be provided to apply the pulse from this one shotpulse generating circuit to the set input of flipflop 2612.

FIG. 111 shows an example of a specific structure of column addressstrobe signal generating circuit 2602 shown in FIG. 109. Referring toFIG. 111, the column address strobe signal generating circuit 2602includes an AND circuit 2621 receiving at its one input clock signal K;an inverter circuit 2622 receiving internal row address strobe signal/RAS; and a flipflop 2623 having a set input /S receiving an output fromAND circuit 2621, a reset input /R receiving an output from invertercircuit 2622, a Q output and /Q output. /Q output of flipflop 2623 isapplied to the other input of AND circuit 2621. Column address strobesignal /CAL is generated from /Q output of flipflop 2623, and columnaddress strobe signal CAL is generated from the inverter circuit 2624receiving /Q output of flipflop 2623.

Flipflop 2623 includes two NAND circuits cross coupled to each other,for example. It is set when a signal at "L" is applied to set input /S,and it is reset when a signal at "L" is applied to reset input /R. Theoperation will be described.

Assume that flipflop 2623 is reset. At this time, /Q output of flipflop2623 is at "H", and output from AND circuit 2621 is at "H" in responseto the rise of clock signal K. When clock signal K falls to "L", theoutput from AND circuit 2621 falls to "L", flipflop 2623 is set, columnaddress strobe signal /CAL from /Q output thereof attains "L" and columnaddress strobe signal CAL from inverter circuit 624 attains "H". Rowaddress strobe signal /RAS attains to "L" in response to the rise ofclock signal K, and output of inverter circuit 2622 attains "H".

After a lapse of a predetermined time periods internal row addressstrobe signal /RAS rises from "L" to "H", and the output from invertercircuit 2622 falls to "L". Consequently, flipflop 2623 is reset, columnaddress strobe signal/CAL attains "H" and column address strobe signalCAL attains "L".

At this time, signals to set input /S and reset input /R of flipflop2623 may be both "L". However, such state can be prevented by providinga structure for resetting /Q output of flipflop 2623. A circuitstructure for setting Q output of flipflop 2623 as well may be provided.

Alternatively, a structure for generating a one shot pulse signal havinga predetermined pulse width in response to a fall of clock signal K toprovide the same to set input /S of flipflop 2623 may be used as asimple method. At this time, the generated one shot pulse signal fallsfrom "H" to "L" upon generation.

FIG. 112 shows an example of a specific structure of row address latch2603 shown in FIG. 109. Referring to FIG. 102, row address latch 2603includes an inverter circuit 2631 receiving external address signal Aa;a clocked inverter 2632 receiving an output from inverter circuit 2631;an inverter circuit 2633 receiving an output from clocked inverter 2632;and a clocked inverter 2634 receiving an output from inverter circuit2633.

Operation of clocked inverter 2632 is controlled by internal row addressstrobe signals RAS and /RAS. When internal row address strobe signal RASis at "H" and internal row address strobe signal /RAS is at "L", clockedinverter 2632 is set to an output high impedance state, which is aninactive state. When internal row address strobe signal RAS is at "L"and internal row address strobe signal /RAS is at "H", clocked inverter2632 is rendered active, and it inverts an output from inverter circuit2631 and transmits the same to a node N10.

Clocked inverter 2634 is rendered active when internal row addressstrobe signal /RAS is at "L" and internal row address strobe signal RASis at "H" and it functions as an inverter. When internal row addressstrobe signal RAS is at "L" and internal row address strobe signal /RASis at "H", clocked inverter 2634 is set to an output high impedancestate, which is an inactive state. Therefore, when clocked inverter 2634is active, inverter circuit 2633 and clocked inverter 2634 constitute alatch circuit, and continuously outputs signal potential appearing onthe node N10. Internal row address signal int.Ara is generated from nodeN10. The operation will be described in the following.

When internal row address strobe signal /RAS is at inactive "H", clockedinverter 2632 functions as an inverter. At this time, clocked inverter2634 is at the output high impedance state. Therefore, at this time,external address signal Aa is transmitted to node N10. When clockedinverter 2632 is set to the output high impedance state, and clockedinverter 2634 is rendered active to function as an inverter. At thisstate, signal potential appearing at node N10 when the internal rowaddress strobe signal /RAS has been "H" is latched by inverter circuit2633 and clocked inverter 2634, and it is continuously output asinternal row address signal int.Ara.

FIG. 113 shows an example of a specific structure of column addresslatch 2604 shown in FIG. 109. Referring to FIG. 103, column addresslatch 2604 includes an NOR circuit 2641 receiving at one input externaladdress signal Aa and at the other input internal row address strobesignal /RAS; a clocked inverter 2642 receiving an output from NORcircuit 2641; an inverter circuit 2643 receiving an output from clockedinverter 2642; and a clocked inverter 2644 receiving an output frominverter 2643.

Clocked inverter 2642 is rendered active and serves as an inverter wheninternal column address strobe signal CAL is at "L" and internal columnaddress strobe signal /CAL is at "H". When internal column addressstrobe signal CAL is at "H" and internal column address strobe signal/CAL is at "H", clocked inverter 2642 is rendered inactive and set tothe output high impedance state. Clocked inverter 2644 is renderedactive and serves as an inverter when internal column address strobesignal /CAL is at "L" and internal column address strobe signal CAL isat "H". When internal column address strobe signal CAL is at "L" andinternal column address strobe signal /CAL is "H", clocked inverter 2644is rendered inactive and set to the output high impedance state. Whenclocked inverter 2644 is active, inverter circuit 2643 and clockedinverter 2644 constitute a latch circuit, which latches a signalpotential appearing at node N20. An internal column address signalint.Arc is generated from node N20. The operation will be described.

When internal row address strobe signal /RAS is at "H", an output fromNOR circuit 2641 is at "L" Since internal column address strobe signalsCAL and /CAL have not yet been generated at this time, clocked inverter2642 serves as an inverter and transmits a signal at "H" to node N20.

When internal row address strobe signal /RAS falls to "L", NOR circuit2641 functions as an inverter. At this time, NOR circuit 2641 outputs aninverted signal of external address signal Aa. After a predeterminedtime period from a fall of the internal row address strobe signal /RASto "L", internal column address strobe signals CAL and /CAL aregenerated, clocked inverter 2642 is set to the output high impedancestate, and clocked inverter 2644 is rendered active and functions as aninverter. Consequently, signal potential appearing at node N20 wheninternal column address strobe signals CAL and /CAL are generated iscontinuously output as internal column address signal int.Arc.

The structures shown in FIGS. 112 and 113 correspond to portions relatedto 1 bit of external address signal Aa. The circuit shown in FIGS. 112and 113 are provided for each bit of each external address signal Aa.

Reset signal generating circuit 2605 shown in FIG. 109 may have anycircuit structure provided that reset pulse RS is generated after apredetermined time period from detection of a fall of internal rowaddress strobe signal /RAS to "L". The reset signal generating circuitcan be readily realized by a circuit structure including a circuit forproviding a delay in row address strobe signal /RAS and a circuit forgenerating a one shot pulse signal in response to the output from thedelay circuit.

The reset signal generating circuit 2605 may have a structure that thereset signal is generated from DRAM array driving circuit 260 shown inFIG. 105. At this time, DRAM array driving circuit 260 generates asignal for activating circuitry of a portion related to row selectingoperation of the DRAM array, and the reset pulse may be generated at atime point when the operation of the circuitry related to row selectionis completed. For example, a structure generating reset pulse RS after apredetermined time period from the generation of a sense amplifieractivating signal for sensing operation in DRAM array 101 may beemployed.

A structure for setting CDRAM to operation modes dependent on intendeduse, that is, high speed operation mode or low power consumption mode,will be described. Command registers are used for setting such modes.

As shown in FIG. 114, operation mode of the CDRAM is set dependent ondata values of data input pins DQ3 (D3) and DQ2 (D2) when a register WR0is selected.

When DQ3 (D3) and DQ2 (D2) are both set to "0", a first high speed modeis designated. By setting DQ3 (D3) and DQ2 (D2) to "0" and "1",respectively, a low power consumption mode is designated. When DQ3 (D3)and DQ2 (D2) are set to "1" and "0", respectively, a second high speedoperation mode is designated. The input terminal is represented as DQ(D) when register WR0 is set, since pin function differs dependent onwhether DQ separation mode is designated by a register RR1 or maskedwrite mode is selected by a register RR0. Operation modes realized bydata AB applied to data DQ3 (D3) and DQ2 (D2) of register WR0 will bedescribed.

FIG. 115 shows a high speed operation mode of the CDRAM. The first highspeed operation mode is selected by setting upper 2 bits of data AB ofregister WR0 both to "0". In this state, a row address signal (ROW) istaken at first at a rising edge of the first clock signal K (#1) of theclock signal K, and then, a column address signal (COL) is taken at arise of a third clock signal K (#3). The operation of the CDRAM isstarted from a falling edge of the third clock signal #3.

The second high speed operation mode is selected by setting the upper 2bits of data AB of the command register WR0 to "1" and "0". In thesecond high speed operation mode, row address signal (ROW) is taken at arising edge of the first clock signal K (#1), and column address signal(COL) is taken at a rising edge of the successively applied second clocksignal K1 (#2).

Therefore, when the DRAM array is to be accessed at a cache miss of theCDRAM or the like, speed of operation can be set at an optimal valuedependent on the intended use. Since time required for accessing theDRAM array can be set at an optimal value dependent on the object ofprocessing, flexible system structure is enabled.

FIG. 116 is a diagram of signal waveforms showing an operation in whichCDRAM operates in the low power consumption mode. The low powerconsumption mode is designated by setting upper 2 bits of AB of commandregister WR0 shown in FIG. 114 to "0" and "1", respectively. In the lowpower consumption mode, row address signal (ROW) is taken at a risingedge of clock signal K, and column address signal (COL) is taken at afalling edge of clock signal K. In this case, row and column addresssignals are taken responsive to a single pulse. Even if the clock signalK is generated intermittently or the period of the clock signal K ismade longer temporarily and therefore the period of the clock is madelonger, row and column address signals can be taken by a single clocksignal. Since DRAM starts its operation immediately after the columnaddress signal is taken, a CDRAM which operates at high speed with lowpower consumption can be provided.

FIG. 117 shows a circuit structure for setting a timing for takingexternal address signal Aa dependent on the operation mode. The circuitstructure shown in FIG. 107 is used as column address strobe signalgenerating circuit 2602 shown in FIG. 109. More specifically, the columnaddress strobe signal generating circuit shown in FIG. 117 is usedinstead of column address strobe signal generating circuit shown in FIG.111. The above described respective circuits may be used for othercircuit structures. Referring to FIG. 117, column address strobe signalgenerating circuit 2602' includes an AND circuit 2701 receiving, at itsone input, clock signal K; and a flipflop 2702 receiving an output fromAND circuit 2701 at its set input /S1 and internal column address strobesignal /RAS at its reset input /R1 through an inverter circuit 2709. Anoutput /Q1 of flipflop 2702 is applied to the other input of AND circuit2701. Flipflop 2702 is set or reset when a signal at "L" is applied toinput /S1 or /R1.

Circuit 2602' further includes an OR circuit 2703 receiving at one inputthe clock signal K, an OR circuit 2710 receiving output /Q1 of flipflop2702 and internal row address strobe signal /RAS; and a flipflop 2704having a set input S2 receiving an output from OR circuit 2703 and areset input R2 receiving an output from OR circuit 2710. An output Q2 offlipflop 2704 is applied to the other input of OR circuit 2703. Flipflop2704 is set when an output from OR circuit 2703 rises to "H", and it isreset when an output from OR circuit 2710 rises to "H".

Circuit 2602' further includes an AND circuit 2705 receiving, at oneinput, clock signal K; an AND circuit 2711 receiving an output Q2 offlipflop 2704 and internal row address strobe signal RAS from invertercircuit 2709; and a flipflop 2706 receiving at a set input /S3 an outputfrom AND circuit 2705 and at a reset input /R3 an output from ANDcircuit 2711. An output Q3 of flip flop 2706 is applied to the otherinput of AND circuit 2705. Flipflop 2706 is set in response to a fall ofa signal applied to set input /S3, and it is reset in response to a fallof a signal applied to reset input /R3.

Circuit 2602' further includes an OR circuit 2707 receiving, at oneinput, clock signal K; an OR circuit 2712 receiving an output /Q3 offlipflop 2706 and internal row address strobe signal /RAS; and aflipflop 2708 receiving at a set input S4 an output from OR circuit 2707and at a reset input R4 an output from OR circuit 2712. An output Q4 offlipflop 2708 is applied to the other input of OR circuit 2707. Flipflop2708 is set in response to a rise of a signal applied to set input S4,and it is reset in response to a rise of a signal applied to reset inputR4.

Column address strobe signal generating circuit 2602' further includesan AND circuit 2715 receiving an Q2 output from flipflop 2704 and data B(corresponding to DQ2 shown in FIG. 114) set in register WR0; aninverter circuit 2713 receiving an output /Q1 from flipflop 2702; an ANDcircuit 2714 receiving an output from inverter 2713 and data A(corresponding to data DQ3 shown in FIG. 104) set in register WR0; an ORcircuit 2716 receiving an output from AND circuit 1714, an output fromAND circuit 2715 and an output Q4 of flipflop 2708; and an invertercircuit 2717 receiving an output from OR circuit 2716. Column addressstrobe signal CAL is generated from OR circuit 2716, and column addressstrobe signal /CAL is generated from inverter circuit 2717. Theoperation will be described with reference to the diagram of signalwaveforms of FIG. 118.

The operation when low power consumption mode is set will be described.At this time, data A is "0" ("L"), and data B is "1" ("H"). In thisstate, an output from AND circuit 2714 is "L". Flipflops 2702, 2704,2706 and 2708 are at reset state. When external clock signal K rises forthe first time, an output from AND circuit 2701 attains "H". At thistime, in flipflop 2702, only a signal applied to set input /S1 risesfrom "L" to "H", and therefore it is kept at the reset state. Inresponse to a rise of clock signal K, internal row address strobe signal/RAS falls to "L". At this time, since flipflop 2702 is kept at thereset state, output /Q1 of flipflop 2702 is at "H", and therefore outputfrom OR circuit 2710 is also at "H".

Even when output from OR circuit 2703 rises to "H" in response to a riseof clock signal K, flipflop 2704 is set by the output from OR circuit2710, so that the output Q2 attains "H". At this time, the output fromAND circuit 2711 is at "L", and the output from OR circuit 2712 is at"H" (the output /Q3 of flipflop 2703 is at "H"), so that flipflops 2706and 2708 are also maintained at the same state as the reset state.Therefore, in this state, an output from AND circuit 2715 is at "L" andthe output from OR circuit 2716 is also at "L".

When clock signal K falls to "L", the output from AND circuit 2701 fallsto "L", flipflop 2702 is set, and output/Q1 of flipflop 2702 falls from"H" to "L". In response, the output from inverter circuit 2713 rises to"H". Since data B is at "H" potential level, the output from AND circuit2715 rises to "H" in response to the fall of output /Q1 of flipflop 2702to "L". Consequently, the output from OR circuit 2716 rises, internalcolumn address strobe signal CAL attains "H" and internal column addressstrobe signal /CAL falls to "L". Consequently, low power consumptionmode in which row address signal and column address signal are taken atthe rising and falling edges of one pulse (#1) of clock signal K can berealized.

A second high speed operation mode in which a row address signal and acolumn address signal are taken at rising edges of respective clocksignals will be described. At this time, data A is set to 1 ("H") anddata B is set to 0 ("L"). At this time, the output from AND circuit 2715is fixed at "L". The output from AND circuit 2714 attains "H" whenoutput Q2 of flipflop 2704 rises to "H". Output Q2 of flipflop 2704rises to "H" when flipflop 2704 is released from the reset state and theoutput from OR circuit 2703 rises to "H". More specifically, flipflop2704 is set when the output of OR circuit 2703 attains "H" in responseto a rise of clock signal K (#2) which is applied after flipflop 2702 isset and /Q1 output thereof attains "L". Therefore, in the second highspeed operation mode, column address strobe signal CAL is set to "H" andinternal column address strobe signal /CAL is set to "L" at a risingedge of the second clock signal K (#2). Thus the second high speedoperation mode is realized.

A first high speed operation mode in which column address is taken at arising edge of the third clock signal K (#3) will be described. In thiscase, data A and B are both set to "0". In this state, outputs from ANDcircuits 2714 and 2715 are both "L". Output Q2 of flipflop 2704 rises to"H" in response to the second rise (#2) of the clock signal K.Consequently, the output from AND circuit 2711 attains "H" and flipflop2706 is released from the reset state. In response to the second fall(#2) of the clock signal K, the output from AND circuit 2705 falls to"L", flipflop 2706 is set, and output Q3 of flipflop 2706 falls to "L".Since output /Q3 of flipflop 2706 falls to "L", the output from ORcircuit 2712 attains "L", and flipflop 2708 is released from the resetstate. When the output from OR circuit 2707 rises to "H" at a third rise(#3) of the clock signal K, the flipflop 2708 is set, and the potentialof output Q4 thereof rises to "H". Consequently, the output of ORcircuit 2716 attains "H". Thus the first high speed operation in whichrow address signal is taken at the rise of the first clock signal K andcolumn address signal is taken at a rise of the third clock signal K isrealized.

In any of the above described operation cycle modes, when internal rowaddress strobe signal /RAS rises to "H" after a lapse of a predeterminedtime period, flipflops 2702, 2704, 2706 and 2708 are all reset.Flipflops 2702, 2704, 2706 and 2708 have the same structure as flipflops2612 and 2623 shown in FIGS. 110 and 111.

As described above, since the CDRAM operates in synchronization withexternal clock signal K, delay of cycle time derived from skews ofaddresses and the like can be prevented, and accurate control can beeffected, compared with a method in which internal clock signals aregenerated by using an address transition detecting circuit.

In addition, by arbitrarily setting timings for taking the columnaddress of the DRAM, a CDRAM which can flexibly corresponds toapplications in which low power consumption is given priority and toapplications in which high speed operation is given priority can beprovided.

The structure for changing timings for taking the column address is notlimited to apply the CDRAM and any semiconductor memory device ofaddress multiplexing type which operates in synchronization with clocksignals can be used to provide the same effect. A structure in which arow address signal and a column address signal are applied to separatepin terminals may be used.

[Specific Operation Cycles]

CDRAM with a low power and a high speed operation modes can providevarious operation cycles similar to those shown in FIGS. 81 through 84B.The relationship between operation cycles and external control signalsis summarized in a table of FIG. 119 and respective operating cycles forthe low power consumption mode and the high speed operation mode aredescribed with reference to FIGS. 120 through 161.

FIG. 119 is a table showing operation modes of the CDRAM in accordancewith the second embodiment of the present invention and states ofcontrol signals for designating respective operation modes. Theoperation modes of the CDRAM are set by various combinations of externalcontrol signals, that is, a chip select signal E#, a cache hit signalCH#, a write enable signal W#, a refresh designating signal REF# andcontrol signals CC1# and CC2#. Referring to FIG. 119, the character "H"represents a high level signal potential, and "L" represents a low levelsignal potential. As shown in FIG. 119, operation modes of the CDRAMinclude a cache mode TH for accessing the SRAM cache; a command registerset mode TG for setting command data in command registers; a standbymode TS for setting the CDRAM to a standby state; a cache miss mode DMfor carrying out operation at a cache miss (miss hit); a direct arrayaccess mode TD for directly accessing the DRAM array; a refresh mode TRfor refreshing the DRAM array; and a counter check mode TC for checkinga counter generating row addresses for refreshing the DRAM array.Combinations of signal states and timings for setting the respectiveoperation modes will be described in detail later with reference todiagrams of signal waveforms. The operation at a cache miss will bebriefly described.

At a time of cache miss, or a miss hit, data requested by the CPU is notstored in the SRAM cache. Therefore, the requested data must betransferred from the DRAM array to the SRAM cache. This transfer is donethrough bi-directional transfer gate circuit (DTB) 210 shown in FIG.105. Data transfer operation will be described with reference to FIG.120. Bi-directional transfer gate 210 includes a transfer gate DTB 2 fortransferring data in DRAM array 101 to SRAM array 201, and a transfergate DTB 1 for latching data from SRAM array 201 and for transferringthe same to DRAM array 101 (see structure of data transfer gate shown inFIGS. 49 and 57).

Assume that data D2 is stored in a region D of SRAM array 201, and CPUrequests data D1 in this region D. This is a cache miss. At this time,in accordance with the address output from the CPU, data D1 is selectedfrom DRAM array 101 and it is transmitted to transfer gate DTB 2. Inparallel, data D2 stored in SRAM array 201 is latched in transfer gateDTB 1. Then, data D1 which has been transferred to transfer gate DTB2 istransferred to a corresponding region D of SRAM array 201. Data D2 islatched in transfer gate DTB 1. After data D1 has been transferred toSRAM array 201, CPU can access SRAM array 201. DRAM array 101 is onceset to a precharge state to receive data D2 from transfer gate DTD 1.Then an address indicating an address in which data D2 is to be storedis applied from, for example, a tag memory to DRAM array 101, and rowselection operation is effected in accordance with this address(hereinafter referred to as a miss address). After the row selectingoperation, data D2 stored in transfer gate DTB 1 is transferred to thecorresponding region.

Since data transfer is done in two directions in parallel as describedabove, even at a cache miss, CPU can access SRAM array 201 forreading/writing desired data immediately after data transfer from DRAMarray 101 to SRAM array 201, without waiting for the DRAM array 101returning to the precharge state. Operations in respective operationmodes (high speed mode, low power consumption mode) during data transferwill be described in detail with reference to FIG. 121, which is adiagram of signal waveforms.

First, by setting chip select signal E# to "L" and cache hit signal CH#to "H" at a rising edge of clock signal K, an initiate cycle TMMI forcache miss cycle TM is effected. In cache miss initiate cycle TMMI, anSRAM address Ac is taken as valid in the device at a rising edge ofclock signal K, and a row address signal (R) out of DRAM address Aa istaken in the device. In low power consumption mode, a column addresssignal (C) of DRAM address Aa is taken successively at a falling edge ofthe clock K. In the second high speed operation mode, the column addresssignal (C) is taken at a rising edge of a third clock signal K.

Then array active cycle TMMA is started at a second rise of clock signalK. In array active cycle TMMA, memory cell selecting operation is donein the DRAM array in accordance with the CPU address, and selectedmemory cell data is transferred to the SRAM array. After the datatransfer from the DRAM array to the SRAM array, memory cells is selectedin the SRAM array in accordance with the SRAM address taken in advance,and selected data Q is output. At this time, the data which has beentransferred from SRAM array to the transfer gate is kept latched in thetransfer gate DTB 1. By this state, array active cycle TMMA iscompleted. It takes time tKHAA from the first rise of clock signal K tothe output of data Q requested by the CPU, and it takes time tCAA fromtaking of the DRAM column address to the output of the requested data Q.

After the completion of the array active cycle TMMA, a precharge cycleTMMP for precharging the DRAM is effected. During this precharge period,SRAM cache can be independently accessed. Chip select signal E# andcache hit signal CH# are set to "H" or "L" dependent on whether the SRAMis accessed or not, and data is output dependent on the accessing stateat this time. Meanwhile, internal precharging operation is effected inthe DRAM array, and various signal lines are precharged to desiredpotentials.

After the completion of precharging of the DRAM array, an array writecycle TMA for writing data which has been transferred from the SRAMarray to the transfer gate DTB 1 to corresponding memory locations ofthe DRAM array is carried out.

Array write cycle TMA is started with an initiate cycle TMAI. Thisinitiate cycle is started by setting chip select signal E# to "L" at arising edge of clock signal K. Consequently, a miss address applied froma tag memory, for example, is applied to the DRAM, and in the DRAMarray, the applied miss address is taken as the row address signal (R)and column address signal (C) dependent on the operation mode. After therow and column address signals are taken, an array write.array activecycle for actually writing the latched data to the DRAM array and theprecharge cycle TMAA are carried out.

In array active-precharge cycle TMAA, a corresponding memory cell isselected from the DRAM array in accordance with the applied missaddress, and data which has been latched in bi-directional transfer gateDTB1 is written to the selected memory cell and then DRAM array issubject to precharging. In parallel to the data writing cycle in theDRAM array, the CPU can independently access the SRAM array.

Cycle time of clock signal K is tK, and array cycle time of the DRAM(necessary for reading desired data by directly accessing the DRAMarray) is represented as TA. The cycle time necessary for the missread/write cycle TMM at a cache miss must be not shorter than arraycycle time ta. Similarly, cycle time of the array write cycle TMA mustbe not shorter than array cycle time ta.

FIG. 122 is a diagram of signal waveforms showing a cache hit readingoperation in the low power consumption mode. FIG. 122 shows the cachehit reading operation (LTHR) in the transparent output mode. The cachehit reading operation is effected by setting chip select signal E# to"L", cache hit signal CH# to "L", control signal CC1# to "L", refreshdesignating signal REF#, control signal CC2# and write enable signal W#to "H" at a rising edge of clock signal K. At this time, SRAM address(CPU address) Ac is taken at the rising edge of the clock signal K andthe SRAM cache is accessed. By making output enable signal G# fall from"H" to "L", data Q1 corresponding to the taken SRAM address C1 is outputafter the lapse of time tKHA from the rising edge of the clock signal K.

In the hit read cycle THR at a cache hit, only the SRAM cache isaccessed, and data is output in the same clock cycle of the clock signalK. Control signal CC1# is set to "L" only in the first hit read cycle,in order to execute a data transfer array write cycle in the DRAM array.A plurality of cycles are necessary as the DRAM array cycle time, andfrom this time on, array write cycle is effected in the DRAM, andtherefore, control signal CC1# is kept at "H" in the subsequent hit readcycle. When output enable signal G# is at "L", an output from the datainput/output circuit shown in FIG. 105 (see also FIG. 37) is transmittedto the data output pin. Therefore, in the second hit read cycle, data Q2corresponding to the address C2 is output after the SRAM address C2 istaken and after the output of invalid data. When output enable signal G#is at "H", the output data pin D/Q is set to the high impedance state.In the following description, the CDRAM is in the masked write mode, andarrangement of a pin M# for receiving masked data and a DQ pin forcommonly carrying out data input/output is shown as an example.

FIG. 123 is a diagram of signal waveforms showing the cache hit writingoperation in low power consumption. The cache hit mode THW is effectedby setting chip select signal E#, cache hit signal CH# and write enablesignal W# to "L" and setting control signals CC1#, CC2# and refreshdesignating signal REF# to "H" at a rising edge of clock signal K. Atthis time, output enable signal G# is set to "H". In this state, SRAMaddress signal C1 is taken at a rising edge of the clock signal K, anddata D1 which has been applied to data input/output pin DQ is taken. Ifit is in the masked write mode, the data which is to be written at thistime can be masked by setting the signal potential applied to data pinM# to "H" or "L". Since access to the SRAM array only is done in thecache hit write mode THW in the cache hit writing operation, the cycletime of the hit write mode THW is the same as the cycle time tK of clocksignal K.

FIG. 124 is a diagram of signal waveforms showing a cache miss readingoperation in the low power consumption mode. The cache miss readingoperation is started with a miss initiate cycle TMMI. This initiatecycle TMMI is started by setting chip select signal E# to "L" and othercontrol signals CH#, CC1#, REF#, CC2#, W# and G# to "H" at a rising edgeof clock signal K. In the initiate cycle TMMI, first an SRAM address Ac1is taken for designating an address of the SRAM array, and, at the sametime, the same address is taken as the DRAM array address signal Aa. Atthis time, 16 bits (16 bits×4) of data are simultaneously transferredfor one memory cycle. Since the output data includes 4 bits, thenecessary address bits except the lower address bits out of the address(CPU Add) applied from the CPU, are applied as the DRAM address signalAa.

For the operation with low power consumption, the DRAM address signal Aais taken as the row address (ROW) at a rising edge of clock signal K,and a column address signal COL is taken at the falling edge of thisclock signal K. At this state, memory cell selecting operation iseffected in the SRAM array and the DRAM array, and corresponding memorycell data are transferred from the DRAM to the SRAM array. Dataselecting operation in the DRAM array is carried out by setting thearray active cycle TMMA. The array active cycle TMMA is designated bysetting all control signals to "H" at a rising edge of clock signal K.

By making the output enable signal G# fall to "L" in array active cycleTMMA, data Q1 selected in accordance with the address signal C1 in theSRAM array is output after a lapse of a predetermined time period. Afterthe completion of the array active cycle in the DRAM array, theoperation must be once changed to the precharge cycle for writing datawhich has been read from the SRAM array and latched in thebi-directional transfer gate circuit to the DRAM array. For setting theprecharge cycle TMMP at a miss read, the same combination of signals asto designate standby or cache hit operation TK is used at a rising edgeof clock signal K. When chip select signal E# is set to "L" whilesetting cache hit signal CH# to "L" at this time, data can be read fromthe SRAM array while the DRAM array is in the precharge cycle.

FIG. 125 is a diagram of signal waveforms showing a cache miss writingoperation in the low power consumption mode. The cache miss writingoperation is realized by setting the chip select signal E# and writeenable signal W# to "L" at a rising edge of clock signal K. At thistime, initiate cycle TMMI for cache miss writing operation is effectedat first. The cache miss writing operation is the same as the cache missreading operation shown in FIG. 124 except that the direction of dataflow is different. After corresponding data are transferred from theDRAM array, or simultaneously with the data transfer, writing of data D1to the corresponding memory cell in accordance with the address signalC1 for the SRAM array is carried out. The only difference between cachemiss writing and cache miss reading is that the write enable signal W#is at "L" or not.

FIG. 126 is a diagram of signal waveforms showing an array writingoperation. In the array writing operation, data which has beentransferred from the SRAM array to the bi-directional transfer gatecircuit to be latched therein is written to the corresponding memorycell of the DRAM array. The array writing operation cycle LTMA includesinitiate cycle TMAI and array active cycle TMAA. The initiate cycle TMAIis set by setting chip select signal E# and control signal CC2# to "L"and control signal CH#, CC1# to "H" at a rising edge of clock signal K.In this initiate cycle TMAI of the array writing operation cycle LTMA inthe low power consumption mode, an address signal (MissAdd) applied froman external device such as a tag memory is taken corresponding to therising and falling edges of the clock signal K, and internal row addressand column address signals are generated responsively. Successive to theinitiate cycle TMAI, chip select signal E# and cache hit signal CH# areset to "L" and control signal CC1# is set to "H" at a rising edge of theclock signal K. Thus array active cycle TMMAA as well as cache hitoperation are set. At this time, when write enable signal W# is set to"L", the SRAM address signal Ac is taken, and data is written to theSRAM cell corresponding to the taken address C2. At this time, maskeddata M# may be applied. In the array active cycle TMAA in the arraywriting operation, DRAM memory cell is selected in accordance with thetaken address, and data which has been latched in the bi-directionaltransfer gate is written to the selected DRAM memory cell.

FIG. 127 is a diagram of signal waveforms showing array writingoperation accompanied with cache hit reading operation. Array writingoperation accompanied with cache hit reading in the low powerconsumption mode is shown, and in this cycle LTMAR, reading of data fromthe SRAM cache is carried out in parallel with data transfer from thebi-directional transfer gate to the DRAM array.

This operation cycle LTMAR is set by setting chip select signal E#,control signal CC1# and cache hit signal CH# to "L" and by settingcontrol signal CC2# and write enable signal W# to "H" at a rising edgeof clock signal K. Since refreshing is not carried out, the refreshdesignating signal REF# is at "H". By the setting of these signals, theinitiate cycle TMAI of the array writing operation is effected togetherwith the cache read cycle THR. More specifically, in this operationmode, the SRAM address signal Ac is taken at first at the rising edge ofthe clock signal K, and corresponding data Q1 is output.

The DRAM address signal Aa is taken as the row address signal and thecolumn address signal at the rising edge and the falling edge of theclock signal K, respectively. An address signal (MissAdd) from anexternally provided tag memory, for example, is applied as the DRAMaddress signal Aa for selecting a memory cell to which the data whichhas been latched in the bi-directional transfer gate is to be written.In this manner, data transfer operation to the DRAM array is carried outin parallel with the cache reading operation of the SRAM array.

The array write cycle is carried out by setting the array active andprecharge cycle DMAA. The array active/precharging operation in thearray writing operation accompanied with cache hit reading is set bysetting chip select signal E# to "L", cache hit signal CH# to "L" andcontrol signals CC1# and CC2# both to "H".

FIG. 128 is a diagram of signal waveforms showing an array writeoperation cycle LTMAW accompanied with cache hit writing in the lowpower consumption mode. The array write operation cycle LTMAWaccompanied with cache hit writing is set by setting chip select signalE#, cache hit signal CH# and control signal CC1# to "L" and settingcontrol signal CC2# and refresh designating signal REF# to "H" at arising edge of clock signal K. By setting the signals to such states,the array write initiate cycle TMAI and hit writing cycle THW are set.In response, the SRAM address signal Ac for selecting the SRAM array istaken at the rising edge of clock signal K, and the DRAM address signalAa is taken at a rising edge of clock signal K.

The DRAM address signal Aa is also taken at a falling edge of the clocksignal K and an internal column address signal is generated. Since it isan array writing operation, the DRAM address signal Aa is not theaddress applied by the CPU for writing data which caused cache miss butthe address MissAdd applied by an external device such as a tag memory.The array write operation cycle LTMAW accompanied with cache hit writingis the same as the array write operation cycle LTMAR accompanied withcache hit reading shown in FIG. 127 except that the state of the writeenable signal W# is different. Namely, data is written to the SRAM arrayin accordance with the CPU address in parallel with transfer of datawhich has been latched in the bi-directional transfer gate to the DRAMarray.

FIG. 129 is a diagram of signal waveforms showing a direct array readoperation cycle LTDR in the low power consumption mode. In the directarray read operation cycle LTDR, the DRAM array can be directly accessedto read the corresponding memory cell data of the DRAM. The direct arrayread operation cycle LTDR is started by setting chip select signal E#and control signal CC1# to "L" and setting control signal CC2# to "H",cache hit signal C1#, write enable signal W# and refresh designatingsignal REF# to "H" at a rising edge of the clock signal K. By settingthese signals to such states, an initiate cycle TDI of the direct readarray cycle LTDR is set.

In the initiate cycle TDI, DRAM address signal Aa is taken as the rowaddress signal (ROW) at a rising edge of clock signal K, andsuccessively, 4 bits of address signals Aac 0 to Aac 3 applied to theSRAM address terminal and the DRAM address signal Aa are taken at afalling edge of the clock signal K. The SRAM address signal is also usedin the direct array read operation from the following reason.

Generally, in array accessing, 16 bits of data are transferredsimultaneously per 1 memory block. In case of a 4M bit DRAM, 16 bits×4data are transferred. Therefore, a total of 16 bits of row addresssignals and column address signals only are applied generally.Therefore, in direct array read operation, SRAM address signals Aac 0 toAac 3 are taken as lower address signals for further selecting 4 bitsfrom 16×4 bits of memory cells. A structure for selecting 4 bits of datafrom the SRAM column decoder in accordance with the taken 4 bits of SRAMaddress signals Aac 0 to Aac 3 may be used. In that case, the dataselected in the DRAM is transmitted and selected through a SRAM bitline. Other structure may be used.

Thereafter, the array active/precharge cycle TDA is executed in whichthe memory selecting operation and the data reading operation in theDRAM array are carried out. For setting the array active/precharge cycleTDA in the direct array read operation, all control signals are set to"H". The output timing of the output data Q1 is determined by outputenable signal G#. Consequently, the direct array read operation cycleLTDR in which the DRAM array is directly accessed to read memory celldata therefrom is completed.

After the completion of the direct array read operation cycle LTDR, bysetting chip select signal E# and cache hit signal CH# to "L" at arising edge of clock signal K, memory cell reading operation inaccordance with the SRAM address signal Ac is effected.

FIG. 130 is a diagram of signal waveforms showing a direct array writeoperation cycle LTDW in the low power consumption mode. In the directarray write operation cycle LTDW shown in FIG. 130, data is directlywritten to the DRAM array in accordance with an external address signal.The direct array write operation cycle LTDW is set by setting chipselect signal E#, control signal CCI# and write enable signal W# to "L"and by setting cache hit signal CH#, refresh designating signal REF#,control signal CC2# and output enable signal G# to "H" at a rising edgeof clock signal K. The direct array write operation cycle LTDW is thesame as the direct array read operation cycle LTDR shown in FIG. 129except that write enable signal W# is set to "L" at a rising edge ofclock signal K. At this time, the data T1 applied at the rising edge ofthe clock signal K is written to the DRAM memory cell selected inaccordance with the DRAM address signal Aa and 4 bits of SRAM addresssignals Aac 0 to Aac 3.

The direct array write operation cycle LTDW includes an initiate cycleTDI and the array active/precharge cycle TDA for actually activating theDRAM array. The array active/precharge cycle TDA is the same as thearray active cycle TDA shown in FIG. 129. After the lapse of the DRAMaccess cycle time ta, the SRAM cache can be externally accessed.

FIG. 131 shows the refresh array operation. In the refresh arrayoperation mode LTR, the DRAM array is refreshed under control of refreshcontrol circuit 292 and counter 291 shown in FIG. 105. In this case, arefresh row address indicating a row to be refreshed is generated fromcounter 291 shown in FIG. 105. The refresh cycle is designated bysetting refresh designating signal REF# to "L" at a rising edge of clocksignal K.

Consequently, a refresh initiate cycle TRI is set, and from the nextrise of the clock signal K, the array active cycle TRA for actuallyrefreshing the DRAM array is executed. In the array active cycle TRA inthe refresh array operation mode LTR, all control signals are set to"H". FIG. 131 shows an example in which cache hit reading operation iscarried out after the completion of refreshing.

FIG. 137 is a diagram of signal waveforms showing the refresh arrayoperation mode accompanied with cache hit reading in the low powerconsumption operation. The refresh array operation is carried out onlyfor the DRAM array, and refreshing of the SRAM array is not necessary.Therefore, in parallel with the refresh array operation, the SRAM arraycan be accessed for reading data. In the refresh array operation modeLTRR accompanied with the cache hit reading is started by setting chipselect signal E, cache hit signal CH# and refresh designating signalREF# to "L" and by setting control signals CC1#, CC2# and write enablesignal W# to "H" at a rising edge of clock signal K.

By the refresh designating signal REF#, refreshing of the DRAM array isdesignated, and by chip select signal E# and cache hit signal C1#, thecache hit operation is designated. At this time, auto-refreshingoperation is carried out in the DRAM array in accordance with an outputfrom a built-in address counter. Successive to the refresh initiatecycle TRI, the DRAM array is refreshed in the array active cycle TRA inaccordance with this refresh row address. In the SRAM array, data isread in accordance with an externally applied address signal Ac.

FIG. 153 is a diagram of signal waveforms showing a refresh operationmode with cache hit reading in low power consumption mode. The refreshoperation mode LTRW accompanied with cache hit writing shown in FIG. 133is the same as the refresh array operation accompanied with the cachehit reading shown in FIG. 132 except that write enable signal W# fallsto "L". In this case, data is written in the SRAM array in accordancewith the address signal Ac, and DRAM array is refreshed in accordancewith the refresh address in the DRAM array.

FIG. 134 is a diagram of signal waveforms showing a counter checkreading operation in the low power consumption mode. The counter checkread operation mode LTCR is an operation mode for testing whether or notthe address counter generating the refresh row address for refreshingthe DRAM array functions properly. The counter check read operation modeLTCR is started by setting chip enable signal E#, control signal CC1#and refresh designating signal REF# to "L" and control signal CC1# andwrite enable signal W# to "H" at a rising edge of clock signal K. In thecounter check read operation mode LTCR, lower 4 bits Aac 0 to Aac 3 ofthe SRAM address signal Ac are taken as the lower 4 bits of the columnaddress signal of the DRAM array at a rising edge of clock signal K ininitiate cycle TCI thereof.

Thereafter, DRAM address signal Aa is taken as a column address signal(upper column address bits) at a falling edge of the clock signal K. Incase of a 4M bit DRAM array, 10 bits of column address signal arenecessary for selecting 4 bits of memory cells. At that time, only 6bits are applied as the column address in the DRAM as described above.Therefore, the remaining 4 bits are taken from the SRAM address signalpins. Then, by setting the respective control signals to "H" at a risingedge of the clock signal K, memory cell selecting operation is carriedout in the DRAM array in accordance with the taken column addresses, andselected memory cell data are read. By comparing the read data withpredetermined data or written data, it can be determined whether or notthe refresh row address counter functions properly.

FIG. 135 is a diagram of signal waveforms showing the counter checkwriting operation in the low power consumption mode. To start thecounter check write operation mode LTCW, chip select signal E#, controlsignal CC1#, refresh designating signal REF# and write enable signal W#are set to "L" and cache hit signal CH# and control signal CC2# are setto "H" at a rising edge of clock signal K. At this time, the states ofcontrol signals in this mode are the same as those in the counter checkread operation mode LTCR shown in FIG. 134 except that the write enablesignal W# is set to "L". After counter check writing operation is set inthe initiate cycle TCI, an array active cycle CTA for actually accessingthe DRAM array is executed. In the array active cycle, an address fromthe refresh row address counter is taken as the row address, externaladdresses Aac 4 to Aac 9 and Aac 0 to Aac 3 are taken as the columnaddress signal to carry out row and column selecting operations, andexternally applied data are written to the selected DRAM memory cells.

FIG. 136 is a diagram of signal waveforms showing a command registersetting operation in the low power consumption mode. The commandregister setting operation mode LTG shown in FIG. 136 is an operationmode for writing desired data to the command register 270 shown in FIG.105. By utilizing the command register setting operation mode LTG, theCDRAM can be set to the low power consumption mode, the first high speedoperation mode, the second high speed operation mode, the masked writemode, DQ separation mode and the like. The command register settingcycle LTG is designated by setting chip select signal E#, controlsignals CC1# and CC2# and write enable signal W# to "L" (or "H"), andsetting refresh designating signal REF# to "H" at a rising edge of clocksignal K. By this setting of the operation mode, a command addresssignal Ar is taken and a corresponding command register is selected. Ifwrite enable signal W# is at "L" at this time, data is written to theregister WR0 for designating write mode/output mode, for example. Ifwrite enable signal W# is at "H", any of the registers RR0 to RR3included in the command register is selected in accordance with thecommand address bits Ar0 and Ar1. FIG. 136 shows writing of data to anyof the command registers WR0 to WR3, as an example. The command registersetting operation mode LTG has its set cycle T1 completed in 1 cycle ofthe clock signal K.

FIG. 137 shows an example of an operation sequence in the CDRAM in thelow power consumption mode. In the operation sequence of FIG. 137, anoperation at a cache miss is shown as an example. When a cache missreading occurs, only the chip select signal E# is set to "L" at a risingedge of clock signal K. Consequently, the initiate cycle TMMI of cachemiss reading is carried out, the SRAM address signal C1 and addresssignal Aa (CPU address) for the DRAM array are taken, and thereafter,the array active cycle TMMA for the time of miss read is effected. Inthe array active cycle and the time of a miss read, memory cell dataselected in the DRAM array are transmitted to the memory cells of theSRAM array, and memory cell data corresponding to the SRAM addresssignal C1 applied at the cache miss is read as the output data Q1 at thelast cycle of miss reading.

In the DRAM array, the remaining precharge cycle TMMP of the miss readoperation cycle TMMR is carried out. In this precharge cycle, the SRAMarray can be accessed by the CPU. In FIG. 137, hit read operation is setsimultaneously with the setting of the precharge cycle, and data Q2 isread in accordance with address signal C2.

Successive to the precharge cycle, an array write cycle for writing inDRAM array data which has been transferred from the SRAM array to thebi-directional transfer gate and has been latched therein is effected.If a hit write cycle is being carried out in parallel, the array writecycle is set by setting chip select signal E#, cache hit signal CH#,control signal CC1# and write enable signal W# to "L" at a rising edgeof clock signal K. Consequently, the DRAM enters the array access cycleTMAA, memory cell selecting operation is carried out in accordance withan address MissAdd from a tag memory, for example, and data istransferred from the bi-directional transfer gate to the selected DRAMmemory cell.

In the SRAM array, data D3 is written to the memory cell selected inaccordance with SRAM address signal C3. In the array write cycle in theDRAM array, hit read cycles are continuously carried out in parallel,and output data Q4, Q5 and Q6 corresponding to SRAM address signals C4,C5 and C6 are output. After the hit reading, generation of clock signalK is stopped to reduce power consumption. This state is shown as astandby state in FIG. 137.

FIG. 138 shows another example of the operation sequence in the lowpower consumption mode. FIG. 138 shows a cache miss writing operationand successive cache hit operation. When a cache miss writing occurs, aninitiate cycle TMMI of the cache miss write cycle is effected. At thistime, chip select signal E# and write enable signal W# are set to "L".Consequently, address signals for selecting memory cells in the SRAMarray and the DRAM array are taken. Thereafter, the array active cycleis effected, and data are transferred from the DRAM array to the SRAMarray.

After the completion of data transfer or in parallel with data transfer,data D1 which have caused cache miss writing is written to thecorresponding location in the SRAM array. After the completion of thearray active cycle, precharge cycle of the DRAM array is carried out. Atthis time, hit read operation THR is effected for the SRAM. After theprecharging operation, an array write cycle for writing, to the DRAMarray, data which has been transferred from the SRAM array to thebi-directional transfer gate is carried out.

In the initiate cycle TMAI in the array write cycle, cache hit cycle THis also carried out simultaneously, and therefore control signal CC1# isset to "L". After the completion of the initiate cycle TMI in arraywriting, the array active and precharge cycle is carried out. Inparallel with this array write cycle, hit writing operation, hit readoperation and hit writing operation are carried out. If the CDRAM is notaccessed after a lapse of a predetermined time period, the cycle of theclock signal K is made longer, or clock signal K is generatedintermittently.

As shown in FIGS. 137 and 138, 2 cycles of clocks signal K are taken forthe DRAM array write cycle. Meanwhile, only 1 clock is necessary foraccessing the SRAM array. Therefore, the CDRAM operates at a relativelylow speed, and low power consumption is given priority to high speedoperation.

FIG. 139 is a diagram of signal waveforms showing cache hit readingoperation in the high speed operation mode. FIG. 139 shows data outputin the transparent output mode for the cache hit read operation mode THRunder the high speed operation mode. The cache hit reading operationmode THR in the high speed operation mode has signal waveforms the sameas those in the cache hit reading operation mode LTHR in the low powerconsumption mode shown in FIG. 122, and therefore detailed descriptionthereof is not repeated. FIG. 139 shows data input/output terminals inthe DQ separation mode. More specifically, input data D and output dataQ are input and output through separate pin terminals.

FIG. 140 shows a diagram of signal waveforms showing cache hit readingoperation in which data is output in latched output mode. The cache hitread operation mode THRL shown in FIG. 140 is carried out in the highspeed operation mode. The combinations of control signals for settingthis operation mode are the same as those shown in FIG. 139. The cachehit read operation mode THR shown in FIG. 139 differs from cache hitread operation mode THRL in the latched output mode in that timings ofoutput data are different. More specifically, in the latched outputmode, data read in the last cycle is output in an invalid data period ofthe waveform of the output data Q shown in FIG. 139. Namely, the dataread in the last cycle is continuously output until valid data is outputin the next cycle. In the latched output mode, invalid data is notoutput, and therefore stable data processing operation is possible.

FIG. 141 is a diagram of signal waveforms showing a cache hit readoperation mode in registered output mode in high speed operation mode.The cache hit read operation mode THRR in the registered output mode isrealized by the same combination of signal states as that for theoperation modes THR and THRL shown in FIGS. 139 and 140. Different fromthe transparent output mode (see FIG. 139) and latched output mode (seeFIG. 140), memory cell data selected in the previous cycle is output insynchronization with clock signal K in the registered output mode. Inthe register output mode, data read in the last cycle is output insynchronization with the clock signal, and therefore it is suitable forpipe line application.

FIG. 142 is a diagram of signal waveforms showing cache hit writingoperation in the high speed operation mode. The cache hit writeoperation mode THW shown in FIG. 142 is realized by the same combinationof signal states as in the cache write operation LTHW in low powerconsumption mode shown in FIG. 123, and therefore, description thereofis not repeated.

FIG. 143 is a diagram of signal waveforms showing cache miss readingoperation in the high speed operation mode. In the cache miss readoperation mode TMMR in the high speed operation mode, the initiate cycleTMMI is completed in 1 clock cycle. However, in the high speed operationmode, the column address is taken at a rising edge of a third clocksignal K. This is the difference from the cache miss read operation modeLTMMR in the low power consumption mode shown in FIG. 124.

FIG. 144 is a diagram of signal waveforms showing cache miss readingoperation in latched output mode in the high speed operation mode. Thecache miss read operation mode TMMRL shown in FIG. 144 is the same asthe cache miss read operation mode TMMR shown in FIG. 144 except thatdata Q0 read in the last cycle is output in a period of the output dataQ in which invalid data were otherwise to be output. Except this point,the operation is the same as FIG. 143.

FIG. 145 is a diagram of signal waveforms showing cache miss readingoperation in the registered output mode in the high speed operationmode. The cache miss read operation mode TMMRR shown in FIG. 145 is thesame as operation modes TMMR and TMMRL shown in FIGS. 143 and 144,except the timing of output of the output data Q. Namely, in the latchedoutput mode, data read in the last cycle is kept continuously output inthe period at which invalid data were otherwise to be output, and aftera lapse of a prescribed time period from the fall of clock signal K, thesignal read in the present cycle is output.

In the registered output mode, data is output in synchronization withclock signal K. If clock signal K rises in a short period of time fromthe fall of output enable signal G#, data read in the last cycle isoutput in response to the rise of clock signal K. Except this point, theoperation is the same as those in FIGS. 143 and 144.

FIG. 146 is a diagram of signal waveforms showing cache miss writingoperation in high speed operation mode. The cache miss write operationmode TMMW shown in FIG. 146 is the same as the cache miss writeoperation mode LTMMW shown in FIG. 125 except the timing for taking theDRAM address signal Aa as a column address signal. In this case also,the array active cycle TMMA is effected after the completion of theinitiate cycle TMMI. After the completion of the array active cycleTMMA, the precharge cycle TMMP is carried out.

FIG. 147 is a diagram of signal waveforms showing array write operationin the high speed operation mode. The array write operation mode TMAshown in FIG. 147 is the same as the array write operation mode LTMA inthe low power consumption mode shown in FIG. 126 except the timing fortaking the column address signal (COL) of the DRAM address signal. Inthe array write operation mode TMA in the high speed operation mode,cache hit write operation is effected prior to column selection in theDRAM. The fact that array write operation is carried out means that datatransfer to the SRAM has already been completed. Therefore, the SRAMcache can be accessed at this time.

FIG. 148 is a diagram of signal waveforms showing array write operationaccompanied with cache hit reading in the high speed operation mode.

The combination of states of control signals in the array writeoperation mode TMAR accompanied with cache hit reading shown in FIG. 148is the same as that in the array write operation mode LTMAR in the lowpower consumption mode shown in FIG. 126 except the timings for takingthe column address signal for accessing the DRAM array.

FIG. 149 is a diagram of signal waveforms showing array write operationaccompanied with cache hit reading in the latched output mode in thehigh speed operation mode. Signal states in the array write operationmode TMARL accompanied with cache hit reading in the latched output modeare the same as those in the array write operation mode TMAR accompaniedwith cache hit reading shown in FIG. 148 except the timing of appearanceof the output data Q. Namely, in the latched output mode, in place ofthe output data Q shown in FIG. 148, data read in the last cycle arecontinuously output in the period in which invalid data were to beoutput. Except this point, the operations are the same.

FIG. 150 is a diagram of signal waveforms showing array write operationaccompanied with cache hit reading in registered output in high speedoperation mode. The array write operation mode TMARR accompanied withcache hit reading shown in FIG. 150 is the same as the array writeoperation modes TMAR and TMARL shown in FIGS. 148 and 149 except theoutput timing of data. In the registered output mode, data read in thelast cycle is output in response to a rise of clock signal K.

FIG. 151 is a diagram of signal waveforms showing array write operationaccompanied with cache hit writing in the high speed operation mode. Thecombination of the states of control signals in the array writeoperation mode TMAW accompanied with cache hit writing shown in FIG. 151is the same as that of array write operation mode LTMAW shown in FIG.128, except the timing of taking the column address signal as an addressfor accessing the DRAM array.

FIG. 152 is a diagram of signal waveforms showing direct array readoperation in the high speed operation mode. The combination of states ofcontrol signals in the direct array read operation mode TDR shown inFIG. 152 is the same as that of the direct array read operation modeLTDR shown in FIG. 129 except the timing of taking the column addresssignal out of the DRAM address signals. Therefore, the descriptionthereof is not repeated.

FIG. 153 is a diagram of signal waveforms showing direct array writeoperation in the high speed operation mode. The combination of states ofcontrol signals in the direct array write operation mode TDW shown inFIG. 153 is the same as that of the direct array write operation modeLTDW in the low power consumption mode shown in FIG. 130 except thetiming of taking a column address signal for accessing the DRAM array.Therefore, the description thereof is not repeated.

FIG. 154 is a diagram of signal waveforms showing refresh arrayoperation in the high speed operation mode. The refresh array operationmode TR shown in FIG. 154 is completely the same as the refresh arrayoperation mode LTR in the low power consumption mode shown in FIG. 131,and therefore the description thereof is not repeated.

FIG. 155 is a diagram of signal waveforms showing refresh operationaccompanied with cache hit reading in the high speed mode. The refreshoperation mode TRR accompanied with cache hit reading shown in FIG. 155is completely the same as the refresh array operation mode LTRRaccompanied with cache hit reading showing in FIG. 132. Therefore, thedetailed description thereof is not repeated.

FIG. 156 is a diagram of signal waveforms showing refresh operationaccompanied with cache writing in the high speed operation mode. Thecombination of states of control signals in the refresh operation modeTRW accompanied with cache writing shown in FIG. 156 is the same as thatof refresh operation mode accompanied with cache hit writing shown inFIG. 133. Therefore, the description is not repeated.

FIG. 157 is a diagram of signal waveforms showing counter checkoperation in the high speed operation mode. The counter check operationmode TCR shown in FIG. 157 is the same as the counter check readoperation mode LTCR in the low power consumption mode shown in FIG. 134except the timings for taking column address signal bits Aac 4 to Aac 9.Therefore, description thereof is not repeated.

FIG. 158 is a diagram of signal waveforms showing counter check writingoperation in the high speed operation mode. The counter check writeoperation mode TCW shown in FIG. 158 is the same as the counter checkwrite operation mode LTCW shown in FIG. 135 except the timings fortaking the column address signal bits Aac 4 to Aac 9, and thecombination of the states of control signals is the same.

FIG. 159 is a diagram of signal waveforms showing command registersetting operation in the high speed operation mode. The combination ofthe states of control signals in the command register setting operationmode TG shown in FIG. 159 is the same as that of the command registersetting operation mode LTG shown in FIG. 136.

As described above, in the high speed operation mode, only the timingsfor taking column address signals for accessing the DRAM array aredifferent when access to the DRAM array is necessary, and variousoperations can be readily realized by the same combinations of thecontrol signals for the respective operation modes in the low powerconsumption mode.

FIG. 160 shows an example of an operation sequence of the CDRAM in thehigh speed operation mode. In the operation sequence shown in FIG. 160,access to the cache (SRAM) is effected in parallel with miss readoperation, when a miss read occurs, as an example. At a time of missread, the SRAM array and the DRAM array are both accessed as in the caseof FIG. 137. At this time, different from the low power consumption modeshown in FIG. 137, the column address signal COL 1 for accessing theDRAM array is taken at a third rising edge of the clock signal. Whendata transfer from the DRAM array to the SRAM array is completedaccording to the miss read operation mode TMM, the precharge cyclestarts in the DRAM array. Before the start of the precharging, readingof data Q1 in accordance with the address signal C1 is completed. Hitread operation is effected in parallel with the precharge cycle.

The hit read operation is shown carried out three times in the prechargecycle. In the high speed operation mode, the clock signal is appliedthree times in the precharge cycle, and signals C2, C3 and C4 areapplied as the SRAM array address signals Ac in the respective clockcycles, so that output data Q2, Q3 and Q4 are output. After thecompletion of the precharging operation, the array Write operation iscarried out. In parallel with the array writing operation, hit writeoperation, hit read operation and hit read operation are shown carriedout in the SRAM array.

Therefore, in the high speed operation mode shown in FIG. 160, theperiod of the clock signal K is short, and data can be read at highspeed by accessing the SRAM array while the DRAM array is beingaccessed.

FIG. 161 shows another example of the operation sequence in the highspeed operation mode. An operation at a time of miss writing is shown asan example. In the operation sequence shown in FIG. 161, the misswriting operation is effected instead of the miss reading operationshown in FIG. 160, and the operation sequence is similar. The hit readcycle, hit read cycle and hit write cycle are shown carried out duringprecharging after the completion of array access, and in the arrayaccess cycle after the completion of the precharging, the hit readcycle, the write cycle and hit read cycle are shown carried out again.

Each operation cycle includes a command register cycle and an arrayactive precharge cycle, and each cycle is determined by the execution ofthe initiate cycle.

[Other Example of Refresh Structure]

(Auto Refresh/Self Refresh Architecture)

In the CDRAM described above, refreshing is externally designated by thesignal REF#. In other words, CDRAM carries out auto-refreshing. There isanother refreshing scheme called self-refreshing in which refresh timingis internally set. In general, an external device is not signaled ofrefreshing timing in the self-refreshing operation. In the following, aconstruction by which refresh timing can be known externally even inself refreshing is described with reference to FIGS. 162 through 175. Inthe described construction, a pin terminal is selectively set to aninput terminal pin for receiving a signal REF# or to an output pinterminal for supplying a signal BUSY# indicating refreshing operation.If the pin serves as the input terminals, auto-refreshing is carriedout. If the pin serves as the output terminal, self-refreshing iscarried out. Such a compatible auto-refreshing/self refreshingarchitecture can also apply to a DRAM.

FIG. 162 shows another example of the refresh method of the CDRAM inaccordance with the present invention. Portions corresponding to thecircuit structure shown in FIG. 32 are denoted by the same referencecharacters in FIG. 162. In the CDRAM structures shown in FIGS. 32 and105, refreshing is carried out in accordance with an externally appliedrefresh designating signal REF#. Namely, only auto-refresh can be donein the CDRAM shown in FIGS. 32 and 105. A structure allowing selfrefreshing in the normal mode will be described.

Referring to FIG. 162, the CDRAM includes a clock generator 3100 takingexternal control signals CR#, CH#, EH# and W# in response to an internalclock int-K from clock buffer 254 for generating various controlsignals; a command register 270a for setting the refresh mode of theCDRAM to auto-refresh or self refresh; and an input/output switchingcircuit 3102 in response to a command signal CM from command register270a for setting a pin terminal 3110 to an input terminal or an outputterminal. The pin terminal 3110 corresponds to the pin terminal of pinnumber 44 shown in FIG. 31. Pin terminal 3110 receives external refreshdesignating signal REF# when it is set as an input terminal. If it isset as an output terminal, pin terminal 3110 outputs a signal BUSY#indicating that self refreshing is being carried out in the CDRAM.

The CDRAM further includes a timer 3101 which is activated in responseto a command from command register 270a for outputting a refresh requestat a predetermined time interval. Clock generator 3100 corresponds tothe control clock buffer 250 and DRAM array driving circuit 260 shown inFIG. 32 or FIG. 105.

FIG. 163 shows a specific structure of clock generator 3100 shown inFIG. 162. Referring to FIG. 163, clock generator 3100 includes an CRbuffer 3200 receiving an externally applied command register set signalCR# for generating an internal control signal int. *CR; a RAS signalgenerating circuit 3201 receiving externally applied control signals CH#and E# and clock signal K for generating an internal control signal int.*RAS; and a CAS signal generating circuit 3202 responsive to internalcontrol signal int. *RAS from RAS signal generating circuit 3201 and toexternal clock signal K for generating an internal control signal int.*CAS.

Internal control signal int. *RAS from RAS signal generating circuit3201 defines operation of the circuitry related to row selectingoperation of the DRAM array. In response to internal control signal int.*RAS, row selecting operation and sensing operation are carried out inthe DRAM array. Internal control signal int. *CAS from CAS signalgenerating circuit 3202 determines operation of the circuitry related tocolumn selection in the DRAM. An example of the circuit related to thecolumn selecting operation in the DRAM array is the DRAM column decoder.

RAS signal generating circuit 3201 contains a circuit for generatinginternal control signal int. *RAS in response to the refresh requestingsignal *BUSY (internal signal) from timer 3101 and to a command signalCM from the command register 270a. In this case, external controlsignals E# and CH# are neglected. A circuit structure for generatinginternal control signal int. *RAS and neglecting external controlsignals, in response to the refresh request (signal *BUSY) from timer3101 is shown in, for example, "64K bit MOS dynamic RAM containingauto/self refresh function", Journal of Institute of Electronics andCommunication Engineers, January 1983, volume J66-C, No. 1.

Internal control signal int. *RAS generated from RAS signal generatingcircuit 3201 and internal control signal int. *CAS generated from CASsignal generating circuit 3202 may be generated from row address strobesignal generating circuit 2601 and column address strobe signalgenerating circuit 2602 shown in FIG. 109 of the second embodiment.

Clock generator 3100 further includes a refresh detecting circuit 3203in response to an externally applied refresh designating signal *REF(this represents internal signal) for detecting designation ofrefreshing; and a refresh control circuit 3204 responsive to a refreshrequest from refresh detecting circuit 3203 for controlling count valueof the refresh address counter 293 and for generating a switching signalMUX for switching connection of multiplexer 258.

Refresh control circuit 3204 also carries out an operation similar tothat executed in accordance with a refresh designation from refreshdesignating circuit 3203 in response to refresh requesting signal(*BUSY) applied from timer 3101, and controls operation of refreshaddress counter 293 and of multiplexer 258. Timer 3101 is activated inresponse to the command signal CM and generates the refresh requestsignal at predetermined time intervals.

In the structure of FIG. 163, instead of applying command signal CM andrefresh requesting signal *BUSY to RAS signal generating circuit 3201, acontrol signal from refresh control circuit 3204 may be applied to RASsignal generating circuit 3201. In that case, RAS signal generatingcircuit 3201 neglects external control signals in response to therefresh designating signal from refresh control circuit, and generatesinternal control signal int. *RAS for a predetermined time period. Afterthe completion of one refresh cycle, refresh control circuit 3204increments the count value of refresh address counter 293 by 1.

FIG. 164 shows an example of a specific structure of input/outputswitching circuit 3202 and command register 270a shown in FIG. 162.Referring to FIG. 164, command register 270a includes a command registerRR2 formed of a 2 bit data register. Command register RR2 takes andstores data applied to data input pins DQ0 and DQ1, when it is selected.The command register RR2 is selected by setting control signals Ar0 andAr1 to "1" and "0", respectively, and by setting external control signalW# to "H" in the command register setting mode (see FIGS. 101, 136 and159), as shown in FIG. 77. A structure of the data input/output pin whenmasked write mode is selected and input and output of data are carriedout through the same pin terminal is shown as an example.

Command register 270a further includes transfer gate transistors Tr 201and Tr 202 for connecting the command register RR2 to data input pinsDQ0 and DQ1. A register selecting circuit 3120 for selecting commandregister RR2 for setting a desired command includes a gate circuit G110receiving register selecting signals Ar0 and Ar1, and a gate circuitG111 receiving internal control signals W, E, CH and int. *CR. Registerselecting circuit 3120 corresponds to command register mode selector 279shown in FIG. 37.

When command selecting signal Ar is at "L" and control signal Ar1 is at"H", gate circuit G110 outputs a signal at "H". The command register RR2is activated when the output from gate circuit G110 attains "H", so asto latch the applied data.

When internal control signal int. *CR and internal chip select signal Eare both at "L" and internal control signals W and CH are at "H", gatecircuit G110 outputs a signal of "H". Therefore, in the command registermode, when gate circuit G111 is selected and output signal therefromattains "H", command register RR2 is connected to data input/outputterminals DQ0 and DQ1 and latches the applied data.

Instead of command register RR2, a command register formed of 1 bitflipflop (for example, RR1 and RR2), in which structure autorefresh/self refresh is set by setting of one flipflop in accordancewith combination of the signals Ar0 and Ar1 in the command registersetting mode.

Input/output switching circuit 3102 includes an NOR circuit G100 and anAND circuit G101 receiving 2 bits of command signals CM from commandregister RR2; a switching transistor Tr200 receiving at its gate anoutput from NOR circuit G100 and passing a signal applied to datainput/output pin 3110; and a switching transistor Tr201 responsive to anoutput from AND circuit G101 for transmitting refresh requesting signal*BUSY from timer 3101 (see FIG. 162) to a terminal 3110.

A signal from switching transistor Tr200 is transmitted to an inputbuffer circuit for the refresh signal for latching a signal in responseto external clock signal K. It is transmitted to transistor Tr201 afterthe output from timer 3101 is buffered. Switching transistors Tr200 andTr201 may be an input buffer and an output buffer, respectively. Whenswitching transistor Tr200 is replaced by an input buffer, the inputbuffer receives not only the output from gate circuit G100 but also asignal applied in response to a rise of the clock signal K.

In the structure of the input/output switching circuit 3102 shown inFIG. 164, NOR circuit G100 outputs a signal at "H" when 2 bits of datafrom command register RR2 are both at "L". AND circuit G101 outputs asignal at "H" when 2 bits of command signals CM are both "1" Therefore,when 2 bits of data DQ0 and DQ1 are both at "0", refresh mode of thesemiconductor memory device is set to the auto refresh mode, and when 2bits of data DQ0 and DQ1 are both "1", the semiconductor memory deviceis set to the self refresh mode.

Other logics may be used for the gate circuits G100 and G101 shown inthe input/output switching circuit 3102. Combinations of values of thebits DQ0 and DQ1 of the command signal CM for designating auto refreshand self refresh may be varied.

A 1 bit command signal may be used as a signal bit for designating autorefresh/self refresh.

FIG. 165 is a diagram of signal waveforms showing the operation of thecircuit shown in FIGS. 162 to 164. The operation will be described withreference to FIGS. 162 to 165.

Assume that data "0" (00) indicating auto refresh is set in accordancewith the command register setting mode, in the command register RR2 ofcommand register 270a. In this case, an output from gate circuit G100attains "H" and an output from AND circuit G101 attains "L".Consequently, input/output switching circuit 3102 switches pin terminal3110 as a signal input terminal. Pin terminal 3110 receives and passesan externally applied refresh designating signal REF#. In the autorefresh mode, an output from timer 3101 is neglected or timer 3101 isreset. In this state, a refresh address and an internal control signalint. *RAS are generated under control of refresh detecting circuit 3203and refresh control circuit 3204 in accordance with externally appliedrefresh designating signal REF#, and the DRAM array is refreshed inaccordance with the generated refresh address.

The command register setting mode is started at time Tx and when "1"(11) is set in register RR2 of command register 270a, an output fromgate circuit G101 attains "H" and an output from gate circuit G100attains "L". Consequently, input terminal 3110 is switched to dataoutput terminal, by the function of the input/output switching circuit3102. Refresh requesting signal *BUSY is transmitted from timer 3101 topin terminal 3110, which is used as a signal representing that selfrefreshing is being carried out in the semiconductor memory device tothe outside of the device.

Timer 3101 is activated in response to the setting of the self refreshmode in command register 270a, and applies a refresh request to refreshcontrol circuit 3204. Refresh control circuit 3204 sets multiplexer 258to a state in which output from refresh address counter 293 is selected,and controls generation of internal control signal int. *RAS from RASsignal generating circuit 3201 in response to the refresh request fromtimer 3101. When the refresh request is applied from refresh controlcircuit 3204, RAS signal generating circuit 3201 generates internalcontrol signal int. *RAS at a predetermined timing.

In accordance with internal control signal int. *RAS, row selectingoperation and sensing operation are carried out in the DRAM, andrefreshing operation for the row designated by the refresh address fromrefresh address counter 293 is carried out. After a lapse of apredetermined time period, an output from timer 3101 rises to "H".Consequently, the refresh period is completed. Refresh control circuit3204 increments address count value of refresh address counter 293 by 1,and stops generation of internal control signal int. *RAS from RASsignal generating circuit 3201.

The period in which the output from timer 3101 is maintained at "L" isset previously. The period in which the output of timer 3101 is kept at"L" is approximately the same as the memory cycle in a common DRAM.After the lapse of this period, timer 3101 resumes its operation, andafter a lapse of a prescribed time period, generates a refresh requestagain and applies the same to refresh control circuit 3204. The DRAMarray is refreshed under control of the refresh control circuit 3204 andRAS signal generating circuit 3201 in accordance with the refreshrequest.

The operation of timer 3101 is continued during designation of selfrefresh by command signal CM. The interval of refreshing of timer 3101may be fixedly set in advance, or it may be programmed in accordancewith the guaranteed time of data retainment of the semiconductor chip.As described above, the semiconductor memory device can be set to theauto refresh or self refresh mode in accordance with command signal CMset in the command register. When refresh designating signal REF# is at"H", the DRAM can be accessed. While refresh designating signal REF# isat "L", timer 3101 does not operate. Refresh operation is controlledexternally. During the refreshing period, the DRAM array can not beexternally accessed.

In self refreshing, refresh execution designating signal BUSY# is outputfrom pin terminal 3110 during refreshing operation in the DRAM array.Therefore, by monitoring refresh execution designating signal BUSY# byan external device, the external device can determine as to whether theDRAM can be accessed, and self refreshing can be carried out in thenormal mode.

The operation can be switched from self refresh to auto refresh byexecuting command register setting mode at a rise of clock signal K andby setting register RR2 of command register 270a to the auto refreshmode (see time Ty of FIG. 165). By so doing, the operation of the timeris inhibited, and auto refresh mode is set in the CDRAM.

By the above described structure, a CDRAM capable of executing autorefresh and self refresh in one chip can be provided. In addition, sinceexecution timing of self refreshing can be known during the normaloperation mode, self refresh can be utilized in the normal operationcycle.

[Modification of Self refresh/Auto refresh]

FIG. 166 shows a modification of the refresh circuit shown in FIG. 152.In the structure shown in FIG. 166, a BBU generating circuit 3210 isprovided, and command signal CM from command register 270a istransmitted to BBU generating circuit 3210.

BBU generating circuit 3210 has a circuit structure for executing abattery backup mode. The BBU mode is described in, for example, "BatteryBackup (BBU) Mode for Reducing Data Retaining Current in a StandardDRAM", Dosaka et al., Journal of Institute of Electronics, Informationand Communication Engineers, 1990, No. 103, ED90-78, pp. 35 to 40, andin "38ns 4M bit DRAM Having BBU Mode", Konishi et al., IEEEInternational Solid States Circuits Conference, 1990 Digest of TechnicalPapers, pp. 230 to 231 and p. 303. In the BBU mode, the number of arraysoperating in the normal mode is reduced to 1/4 in the battery backupmode of a standard DRAM so as to enable refreshing with low current toretain data.

Self refreshing is executed in the BBU mode. The BBU mode will bebriefly described.

FIG. 167 is a diagram for illustrating the BBU mode. A DRAM array DRMAincludes 32 small blocks MBA 1 to MBA 32. The DRAM array DRMA is furtherdivided into memory block groups MAB 1 to MAB 4 by 8 small blocks. Onesmall block is driven or activated in one group. This structurecorresponds to the structure of FIG. 10. Array drivers MAD 1 to MAD 4for driving the DRAM array are provided for the memory array blockgroups MAB 1 to MAB 4, respectively. A BBU control circuit BUC isprovided for driving array drivers MAD 1 to MAD 4.

BBU control circuit BUC transmits a refresh requesting signal to one ofarray drivers MAD 1 to MAD 4 when a control signal REFS is applied. Therefresh requesting signal REFR is successively transmitted to arraydrivers MAD 1 to MAD 4 from BBU control circuit BUC. Array drivers MAD 1to MAD 4 drive one block in corresponding memory array groups MAB 1 toMAB 4, respectively. A row address signal (for example, RAS) appliedfrom a path, not shown, determines which block is to be selected. In thenormal mode, one block is selected from each of the memory array groupsMAB 1 to MAB 4. Namely, four blocks (in the figure, memory blocks MBA 8,MBA 16, MBA 24 and MBA 32) are driven.

In the BBU mode, only one memory array group is driven and only onememory block is driven (in the shown example, memory array block MBA32). Compared with the normal mode, the number of driven blocks isreduced to 1/4, and thus current consumption in refreshing can beconsiderably reduced. The structure shown in FIG. 166 utilizes the BBUgenerating circuit (included in BBU control BUC).

FIG. 168 shows an example of a specific structure of the BBU controlcircuit BUC. Referring to FIG. 168, timer 3101 includes a ringoscillator 3121 oscillating at prescribed intervals, and a binarycounter 3122 counting pulse signals from ring oscillator 3121 forgenerating a signal every prescribed period. Binary counter 3122generates signals for determining refresh timing (for example, every 64μs in self refreshing) and maximum counter value for example, 16 ms;specification value of the refresh cycle).

BBU control circuit BUC further includes a BBU signal generating circuit3210 which start its operation in response to command signal CM and isactivated in response to count up signal CUP 1 from binary counter 3122for generating a battery backup mode designating signal BBU; and a REFSgenerating circuit 3123 responsive to the signal BBU from BBU signalgenerating circuit 3210 and to a refresh cycle defining circuit CPU 2from binary counter 3122 for generating a refresh requesting signalREFS.

BBU signal generating circuit 3210 is activated in response to selfrefresh designation of command signal CM and waits for application ofcount up signal CUP 1 from binary counter 3122. BBU signal generatingcircuit 3210 is rendered inactive when command signal CM designates thenormal mode or the auto refresh mode, and it resets refresh timer 3101.

Upon reception of count up signal CUP 1, BBU signal generating circuit3210 generates the signal BBU. The signal BBU indicates that the CDRAMis switched to the battery backup mode. REFS generating circuit 3123 isactivated in response to the signal BBU, and generates refreshrequesting signal REFS every time refresh cycle defining signal CUP 2 isapplied from binary counter 3122.

FIG. 169 shows a circuit structure for generating internal controlsignal int. *RAS. In the structure of FIG. 169, only the circuitstructure for generating internal control signal int. *RAS out of RASsignal generating circuit 3201 and refresh control circuit 3204 shown inFIG. 163 is shown. RAS signal generating circuit 3201 includes a gatecircuit (NOR circuit) G301 receiving the signals *RAS and BBU; aninverter circuit G302 receiving an output from gate circuit G301; and agate circuit G303 receiving an output from inverter circuit G302 andrefresh requesting signal RASS from refresh control circuit 3204. Gatecircuit G301 generates a signal at "H" when signals applied to bothinput thereof are at "L". Gate circuit G303 generates a signal at "H"when one input thereof is at "L".

The signal *RAS denotes an array access designating signal which isdetermined by signals E and CH which are taken in the device at a risingedge of clock signal K in the CDRAM to which the present invention isapplied. This signal may be generated from the row address strobe signalgenerating circuit shown in FIG. 109.

Refresh control circuit 3204 includes a delay circuit 3231 for providinga prescribed delay to internal control signal int. *RAS; and a RASSgenerating circuit 3232 responsive to refresh requesting signal REFSfrom REFS generating circuit 3123 and to an output signal *SC of delaycircuit 3231 for generating refresh designating signal RASS. The signal*SC from delay circuit 3231 represents completion of sensing, which isgenerated when sensing operation in the DRAM is completed and data ofthe memory cell to be refreshed is surely latched by the senseamplifier. RASS generating circuit 3232 renders active the internalcontrol signal int. *RAS in response to refresh requesting signal REFS,and renders internal control signal int. *RAS in response to thegeneration of sense completion signal *SC.

The operation of the circuit shown in FIGS. 168 and 169 will bedescribed with reference to FIG. 170 which is a diagram of signalwaveforms.

The signal *RASS plays the role of *RAS in the BBU mode. When refreshrequesting signal REFS is generated from REFS generating circuit 3123,signal *RASS from RASS generating circuit 3232 rises to "L" and isactivated. In response, internal control signal output from gate circuitG303 rises to "H", and internal control signal int. *RAS output frominverter circuit G304 attains active "L".

Row selecting operation and sensing operation are carried out in theDRAM in accordance with internal control signal int. *RAS. After thecompletion of sensing operation, sense completion signal *SC from delaycircuit 3231 falls to active "L".

In response to the fall of the sense completion signal *SC, RASSgenerating circuit 3232 raises output signal *RASS. In response,internal control signal int.RAS attains active "H", and thus refreshcycle in the DRAM is completed.

More specifically, in the BBU mode, a rise (transition to the activestate) of refresh requesting signal REFS from REFS generating circuit3123 is used as a trigger for carrying out a self-timed refreshing. Byapplying the signal BBU to gate circuit G301, array access is requestedin the BBU mode, and even if *RAS is rendered active "L", the outputfrom gate circuit G301 is kept at "L", whereby entrance to the arrayactive cycle in the BBU mode is prevented. Although active level of thesignal BBU is not shown, the signal BBU attains "H" when the BBU mode isdesignated.

FIG. 171 shows an example of a specific structure of RASS generatingcircuit 3232 shown in FIG. 169. RASS generating circuit 3232 is formedby a set-reset type flipflop. The flipflop receives refresh requestingsignal REFS at its set input, and receives a sense completion signal *SCat its reset input /R. Signal *RASS is generated from /Q output thereof.Flipflop FFR is set in response to a rise of a signal applied to the setinput S, and its /Q output becomes "0". It is reset in response to afall of a signal applied to its reset input /R and its Q output becomes"H".

[Application to Other Structures]

The above described structure shows an application to the CDRAM.However, this structure can be applied to a general dynamic typesemiconductor memory device containing the DRAM array only. A commondynamic semiconductor memory device receives a row address strobe signal*RAS, a column address strobe signal *CAS and a write enable signal WEas external control signals. Switching between auto refresh and selfrefresh can be done in the dynamic semiconductor memory device receivingexternal control signals *RAS, *CAS and *WE.

FIG. 172 shows a circuit portion related to refresh mode setting circuitin a common dynamic semiconductor memory device. Referring to FIG. 172,the circuitry related to refreshing includes a command register 3502receiving and latching an externally applied refresh mode designatingsignal *CR; an input/output switching circuit 3501 responsive to acommand signal (refresh mode setting signal) CM set in command register3502 for setting a terminal 3510 to an input terminal or an outputterminal; and a clock generator 3503 receiving external control signals*RAS, *CAS, *WE and a refresh designating signal *REF when terminal 3510is used as an input terminal, and receiving command signal CM fromcommand register 3502 for generating various internal control signals ofthe semiconductor memory device and for controlling refreshingoperation.

The dynamic semiconductor memory further includes a refresh addresscounter 3504 responsive to a control signal from clock generator 3503for generating a refresh address; a row address buffer 3506 for passingone of externally applied addresses A0 to A9 and the outputs of refreshaddress counter 3504 for generating internal row address signals RA0 toRA9; and a column address buffer 3507 receiving externally appliedaddress signals A0 to A9 for generating internal column address signalsCA0 to CA9. Timings for taking respective address signals at the rowaddress buffer 3506 and column address buffer 3507 are determined by aninternal control signal from clock generator 3503. The timing for takingexternal row address signals A0 to A9 at the row address buffer 3506 isdetermined by external control signal *RAS, and timings for takingexternal address signals A0 to A9 of column address buffer 3507 isprovided by external control signal *CAS.

Row address buffer 3506 includes not only a simple buffer circuit butalso a multiplex circuit, though not explicitly shown. The multiplexcircuit may receive external row addresses A0 to A9 and an output fromrefresh address counter 3504 to selectively transmit one of these to thebuffer circuit. The multiplex circuit may receive row addresses A0 to A9after the external addresses are converted to internal row addresses.

FIG. 173 shows an example of a specific structure of clock generator3503 shown in FIG. 172. Referring to FIG. 173, clock generator 3503includes a refresh detecting circuit 3510 receiving refresh designatingsignal *REF for determining whether or not there is a refreshdesignation; a RAS buffer 3511 receiving external control signal *RASfor generating internal control signal int. RAS; and a CAS buffer 3512receiving external control signal *CAS for generating internal controlsignal int. CAS. When refresh detecting circuit 3510 detects a refreshdesignation, RAS buffer 3511 and CAS buffer 3512 are rendered inactive.When timer 3505 outputs a refresh request, buffers 3511 and 3512 are setto a signal input prohibited state under the control of refresh controlcircuit 3513 (the signal path in this case is not shown).

Clock generator 3503 further includes a pulse generating circuit 3514responsive to refresh designation from refresh detecting circuit 3510and refresh control circuit 3513 for generating an internal pulse signalhaving a prescribed width; and a gate circuit 3515 receiving internalcontrol signal RAS from RAS buffer 3511 and pulse generating circuit3514. Internal control signal int. RAS is generated from gate circuit3515. The active period of the pulse generated by pulse generatingcircuit 3514 is the period necessary for the completion of refreshing inthe DRAM. When a refresh request is generated from timer 3505, refreshcontrol circuit 3513 generates a switching signal MUX to multiplexer(included in row address buffer 3506) so as to select the output fromrefresh address counter, and activates pulse generating circuit 3514 forgenerating a pulse signals at a prescribed timing.

Timer 3505 starts its operation in response to command signal CM fromcommand register 3502 as in the above described embodiment, andgenerates pulse signals (refresh request signals) at prescribedintervals.

When auto-refreshing is designated by command signal CM, refresh controlsignal 3513 neglects the output from timer 3505, and carries outnecessary control for refreshing in response to the output from refreshdetecting circuit 3510. When command signal CM designates selfrefreshing, refresh control circuit 3513 carries out necessary controloperations for refreshing of DRAM in accordance with the refresh requestfrom timer 3505.

Returning to FIG. 172, the structure of the command register 3502 andinput/output switching circuit 3501 is the same as that shown in FIG.164. In this case, it is not necessary for the command register 3502 tolatch refresh mode setting signal *CR in synchronization with the clocksignal K, and it latches control signals applied at arbitrary timing.The refresh mode setting signal *CR applied externally may be a 1 bitsignal or 2 bit signal. By the above described structure, autorefreshing and self refreshing are both available in a common DRAM. Bythe function of input/output switching circuit 3501, one pin terminal3510 can be switched to input terminal or output terminal. When pinterminal 3510 is set to an output terminal, it represents that selfrefresh is being carried out in the semiconductor memory device. In theself refresh mode, refresh requesting signal from timer 3505 is outputas refresh execution designating signal *BUSY. Therefore, by monitoringthe signal *BUSY, the timing of refreshing can be known by an externaldevice.

By the structure of FIG. 172, a dynamic semiconductor memory deviceallowing self refreshing in the normal mode can be provided, in a commonDRAM.

Further, a BBU generating circuit may be further connected as shown inFIG. 166 to the structure of the dynamic semiconductor memory deviceshown in FIG. 172.

In the structures shown in FIGS. 162, 166 and 172, the self refresh modeand the auto refresh mode can be selectively executed. When the outputfrom command register 3502 has its level fixed by wire bonding, forexample, pin terminal 3510 is fixedly used as an input terminal or anoutput terminal. Therefore, a semiconductor memory device (dynamic typesemiconductor memory device or CDRAM) capable of auto refreshingoperation only or a semiconductor memory device (dynamic typesemiconductor memory device or a CDRAM) capable of self refreshing onlycan be optionally provided. Namely, semiconductor memory devices whichcan accommodate self refresh mode and auto refresh can be provided byone common of the semiconductor chip.

Especially by the structure realizing the auto refresh and the selfrefresh mode on the same semiconductor chip, the guaranteed time of dataretainment of the chip can be measured by using the auto refresh mode inthe refresh interval program necessary when the self refresh is set, andtherefore self refresh cycle period can be set exactly.

When the auto refresh or the self refresh is to be fixed, it is notnecessary to independently and separately provide an input/outputswitching circuit, and the pin terminal (for example, terminal 3510 inFIG. 172) may be set as an input terminal or the output terminal byinterconnections. This structure is shown in FIGS. 174 and 175. In thestructure of FIG. 174, refresh mode designating command CM set byrefresh mode setting circuit 3550 is set to the supply voltage Vcc orground potential Vss by wiring. In this structure, input/outputswitching circuit 3102 is fixedly set to an input circuit or an outputcircuit.

In the structure shown in FIG. 175, refresh mode setting circuit 3550 isset to the auto refresh mode or the self refresh mode by wiring, as inthe structure of FIG. 174. Input/output switching circuit 3551 is set toa signal input circuit or a signal output circuit by wiring, as shown bythe dotted lines.

In the above described structures also, signal BUSY#0 is externallyoutput in the self refresh mode, and therefore self refresh can becarried out in the normal mode.

[Another Embodiment of Address Allottance]

In the CDRAM, the row address and the column address are applied as DRAMaddress Aa time division multiplexedly, as described previously.However, even if the period of the external clock K is made longer(including intermittent generation), it is preferred to operate theCDRAM at a speed as high as possible. A structure for operating theCDRAM at high speed will be described. The following structure whichwill be described with reference to FIGS. 177 to 185 is anotherembodiment of address allotting method shown in FIGS. 71 and 72.

FIG. 176 shows a further embodiment of the address allotting method. Inthe structure shown in FIG. 176, an internal address int. Ac from anaddress buffer 4001 is also applied to DRAM column decoder 103. Namely,a part of the DRAM column address and the SRAM address are shared.

Address buffer 255 shown in FIG. 32 or address generating circuit 360shown in FIG. 105 may be used as address buffer 4001. In the structureshown in FIG. 176, by applying a row address as an address Aa externallyand by applying a column address as an address Ac, the DRAM address canbe provided in non multiplexed manner without increasing the number ofexternal pin terminals. Therefore, timings for taking column address ofthe DRAM can be made faster than in the multiplexing method, and thespeed of operation of the DRAM can be increased. The structure forutilizing the SRAM address and the DRAM address will be described indetail.

FIG. 177 shows more specifically the structure in which SRAM address andDRAM address are commonly used. Referring to FIG. 177, address buffer4001 includes a buffer circuit 4010 receiving external column addresssignals Ac0 to Ac3 for the SRAM for generating an internal columnaddress signal; a buffer circuit 4011 receiving external address signalsAc4 to Ac11 for generating internal address signals; and a buffercircuit 4012 receiving external address signals Aa0 to Aa9 forgenerating internal row address signals for the DRAM. The buffercircuits 4010, 4011 and 4012 latches external addresses and generatesinternal address signals in response to internal clock signal int. K orstrobe signals RAS, /CAL.

An internal address signal from buffer circuit 4010 is applied to SRAMcolumn decoder 203. An internal address signal from buffer circuit 4011is applied to a determining circuit 4020. An internal address signalfrom buffer circuit 4012 is applied to DRAM row decoder 102.

Determining circuit 4020 determines whether the address signal frombuffer circuit 4011 is to be applied to SRAM row decoder 202 or DRAMcolumn decoder 103, in accordance with chip select signal E and cachehit designating signal CH (these signals may be internal signals orexternal signals).

When the SRAM array is accessed, determining circuit 4020 applies theinternal address signal from buffer circuit 4011 to SRAM row decoder202. When the DRAM array is accessed, determining circuit 4020 appliesthe address signal from buffer circuit 4011 to DRAM column decoder 103.

In the structure shown in FIG. 177, out of columns selected by DRAMcolumn decoder 103 in the DRAM array, 4 bits (in case of 4M CDRAM) arefurther selected, by an output from SRAM column decoder 203.

In the structure shown in FIG. 177, address signals Aa0 to Aa9 are usedas array row address signals for designating a row of the DRAM array.Address signals Ac0 to Ac3 are used as cache column address signals fordesignating a column in the SRAM array and as array column addresssignals in direct access to the DRAM array. Address signals Ac4 to Ac9are used as cache row address signals for designating a row in the SRAMarray, and an array column address signals for designating columns inthe DRAM array.

By the structure in which address signals Ac0 to Ac11 and Aa0 to Aa9 canbe independently applied and buffer circuits 4010, 4011 and 4012simultaneously take applied address signals and generate internaladdress signals, as in the structure of FIG. 177, the row addresssignals and column address signals for the DRAM array can besimultaneously taken, and therefore access time in the DRAM array can besignificantly reduced.

FIG. 178 shows an example of a specific structure of determining circuit4020 shown in FIG. 177. Referring to FIG. 178, determining circuit 4020includes a gate circuit G400 receiving internal chip select signal E andinternal cache hit designating signal CH (which is generated fromcontrol clock buffer 250 shown in FIG. 32 or 105); and switchingtransistors Tr400 and Tr401 which are selectively turned on in responseto an output from gate circuit G400. Switching transistor Tr400transmits address signals from buffer circuit 4011 (see FIG. 177) toSRAM row decoder 202. Switching transistor Tr401 transmits internaladdress signals Ac4 to Ac11 to DRAM column decoder 103.

Gate circuit G400 generates a signal at "H" when both inputs thereof areat "L". The signals E and CH are both at "L" at a time of cache hit,that is, the time of accessing to the SRAM array. In that case,switching transistor Tr400 turns on, and internal address signals Ac4 toAc11 are transmitted as SRAM row address signals to SRAM row decoder202.

When the DRAM array is accessed, signal CH# attains to "H", and henceoutput of gate circuit G400 attains "L". Switching transistor Tr401turns on and internal address signals Ac4 to Ac11 are transmitted toDRAM column decoder 103.

In the structure of determining circuit shown in FIG. 178, addresssignals can not be simultaneously transmitted to the DRAM and the SRAMin the block transfer mode and in the copy back mode. A structure inwhich switching transistors Tr400 and Tr401 are both turned on when theblock transfer mode and the copy back mode are designated may beadditionally provided in this case. Such a structure can be easilyimplemented by referring to the combination of the control signals shownin FIG. 76 or 215.

In the structures shown in FIGS. 177 and 178, SRAM address signal linesAc4 to Ac11 are branched into DRAM address signal lines and SRAM addresssignal lines. In this case, load capacitance associated with SRAMaddress signal lines connected to SRAM row decoder is increased. If theload capacitance associated with the SRAM address signal line isincreased, signal delay occurs, an access time at a time of cache hit isincreased. Therefore, load of the SRAM address line must be as small aspossible. A structure for preventing increase of load capacitanceassociated with the SRAM address signal line is shown in FIG. 179.

Referring to FIG. 179, SRAM row decoder 202 includes a predecoder 4051for pre-decoding internal address signals from address buffer 4010; anda SRAM row decoder 4052 for further decoding the pre-decoded signalsfrom predecoder 4051 for selecting a word line in the SRAM array. Themethod of pre-decoding addresses described above is employed in commonsemiconductor memory devices in view of reduction in occupied area ofthe address signal lines and reduction of decoder circuit scale.

In such a structure as shown in FIG. 179, a pre-decoded signal frompredecoder 4051 is transmitted to the DRAM column decoder as shown in(i) of FIG. 169. In this case (I), the length of SRAM address signallines from address buffer 4010 can be made shorter, and delay in addresssignals can be reduced.

The SRAM word line selecting signal from SRAM row decoder 4052 may beapplied to the DRAM column decoder (see case (II) of FIG. 179). When theSRAM word line selecting signal from SRAM row decoder 4052 is to beapplied to the DRAM column decoder, the DRAM column decoder is simplycomprised of a common buffer. In the case (II), since word line drivingcircuit are provided for respective SRAM word lines for driving the SRAMword lines, signal transmission delay is not generated on the SRAM wordlines.

In the structure shown in FIG. 179, the influence of delay incidental todetermining operation in determining circuit 4020 on the access time ofSRAM array can be reduced. More specifically, determination as towhether DRAM array is accessed or SRAM array is accessed takes some timein the determining circuit 4020. In order to carry out cache hitoperation at a high speed, the influence of time necessary fordetermining operation in determining circuit 4020 on the accessing tothe SRAM array must be reduced.

Speed of operation in the DRAM array is not so high as in the SRAM.Therefore, the time for determination in the determining circuit 4020does not affect the column selecting operation in the DRAM array.Therefore, by the structure shown in case (I) or (II) of FIG. 179 inwhich the SRAM address signal line and the DRAM column address signallines are branched after the predecoder circuit 4051, any adverseinfluence to the access time for the SRAM array can be surelyeliminated.

In the structure shown in FIG. 179, determining circuit shown in FIG.178 may be provided at the branching point. Alternatively, signal linessuccessive to predecoder 4051 may be branched directly to SRAM signallines and DRAM signal lines. In this case, address signals (pre-decodedsignal or the SRAM word lines selecting signal) are directly transmittedto the DRAM column decoder. The operations of the DRAM row decoder, DRAMcolumn decoder and the SRAM column decoder are controlled by determiningcircuit 4030 shown in FIG. 180. SRAM row decoder 202 is adapted tooperate when the SRAM array is accessed and the DRAM array is accessed.In the SRAM row decoder 202, where address signal lines are branched atthe output stage of predecoder 4051, the predecoder operates, andoperation of SRAM row decoder 4052 is controlled by determining circuit4030. Where signal lines are branched at the output stage of SRAM rowdecoder 4052, SRAM row decoder 4052 operates until determination bydetermining circuit 4030 is completed.

Even if the SRAM decoder is commonly used for selecting a column in theDRAM array and a column in the SRAM array, only the bit line pair in oneof the arrays is connected to the internal data line, and thereforecollision of data does not occur (see FIGS. 33, 49 and 57). A structurefor controlling driving of the SRAM array and the DRAM array by thedetermining circuit is shown in FIG. 180.

Referring to FIG. 180, determining circuit 4030 receives internalcontrol signals W, E, CH, CI and CR and controls operations of DRAMarray driving circuit 260 and SRAM array driving circuit 264 inaccordance with combinations of the control signals. Command registerset signal CR is also applied to determining circuit 4030 becausecommand register setting signal CR (CC2) is used when high speed copyback operation mode is set, as will be described later. By the structureof FIG. 180, row and column selecting operations in the DRAM array andthe SRAM array can be carried out in parallel. Row and column selectingoperations in the SRAM array and the DRAM array can be executed bytaking addresses in parallel in the block transfer mode, the copy backmode and the like.

The operation in this method of commonly using addresses will bedescribed.

FIG. 181 shows timings of operations at a cache miss. At a time of acache miss, external control signal E# is set to "L" and cache hitdesignating signal CH# is set to "H" at a rising edge of clock K.Consequently, a cache miss is set. External address signals Aa and Acapplied at a rising edge of clock signal K are taken as a row addresssignal (R) and a column address signal (C) of the DRAM. Consequently,the initiate cycle TMMI is executed. Subsequent to the initiate cycleTMMI, array active cycle TMMA is carried out, and data selectingoperation is carried out in the DRAM in accordance with the applied rowaddress signal (R) and the Column address signal (C). Block transfer orhigh speed copy back mode operation may be carried out in the arrayactive cycle TMMA. By setting chip select signal E# to "L" at a risingedge of clock signal K in the last period of the array active cycleTMMA, data Q corresponding to the applied address signals R and C isoutput (When data reading operation is set).

In data writing, by setting chip select signal E# and write enablesignal W# (not shown) to "L" in the initiate cycle TMMI, write data iswritten to the SRAM array as well as to the DRAM array.

When the array active cycle TMMA is completed, the precharge cycle TMPis carried out and the DRAM array is set to the precharge state. In theprecharge cycle TMMP, the SRAM array can be accessed. Internal addresssignal Ac is taken as the SRAM address signal at a rise of clock signalK and a corresponding memory cell in the SRAM array is accessed.

Thereafter, the array write cycle TMA is executed, and data istransferred from the SRAM array to the DRAM array (copy back; transferof latched data to the DRAM array). The array write cycle TMA includesan initiate cycle TMI and an array active cycle TMMA. In the arrayactive initiate cycle TMAI, chip select signal E# is set to "L" at arising edge of clock signal K, and externally applied addresses Aa andAc are taken as the row address signal (R) and column address signal(C). Thereafter, in the array write cycle TMA, corresponding data of theSRAM array latched in a latch circuit is transferred to the DRAM array.Data transfer from the latch to the DRAM array is carried out in thearray active cycle TMMA.

In the array write cycle TMA, data transfer from the latch circuit (seeFIGS. 49 and 57) to the DRAM array is carried out, and therefore theSRAM array can be accessed. The access to the SRAM array in the arrayactive cycle TMMA is shown in FIG. 181 as the address signal Ac beingvalid (V). Consequent to the cache miss cycle TM, a cache hit cycle THor a standby cycle TS is carried out.

Specific reading operation and writing operation will be described. FIG.182 shows timings of operations at a miss read. FIG. 182 shows a clockperiod of 20 ns as an example. In case of a miss read, only the chipselect signal E# is set to "H" at a rising edge of clock signal K. Atthis time, addresses (ROW 1 and COL 1) applied from a CPU (externaloperational processing unit) are taken as the row address signal and thecolumn address signal for the DRAM array. In this miss read operation,the DRAM array is accessed in accordance with the row address signal ROW1 and COL1. Data transfer from the DRAM array to the SRAM array may becarried out during this operation. In this case, the same addresses areapplied to the SRAM array and the DRAM array. In miss operationsaccompanied with data transfer from the DRAM array to the SRAM array,the structure of determining circuit 4030 shown in FIG. 180 is employed.If the structure of determining circuit 4020 shown in FIG. 177 is used,address signal Ac may be taken in accordance with the rising of thesecond clock signal K to carry out row selecting operation of the SRAMarray. After a lapse of a prescribed time period, output enable signalG# is made to "L". When the output enable signal G# falls to "L", dataQ1 corresponding to the applied addresses ROW1 and COL1 is output.

Thereafter, precharge cycle of the DRAM array is carried out. In theprecharge cycle, SRAM array can be accessed. Simultaneously with thestart of the precharge cycle, hit read operation starts in FIG. 182. Inthe hit read operation, chip select signal E# and cache hit designatingsignal CH# are both set to "L" at a rising edge of clock signal K.Accordingly, address signal Ac is taken as a signal for selecting a rowand a column in the SRAM array and the corresponding memory cell data Q2is output in that clock cycle. Referring to FIG. 182, a hit read and ahit read are continuously executed. In respective hit read cycles,output data Q3 and Q4 are output in accordance with addresses C3 and C4.

After the completion of the precharge cycle of the DRAM array, the arraywrite cycle is carried out. In this array write cycle, correspondingdata in the SRAM array has been already latched at the time of missread, and the latched data is transferred to the DRAM array. The arraywrite cycle is set by setting chip select signal E# to "L", cache hitdesignating signal CH# to "H", control signal CC1# (corresponding tocache access inhibiting signal CI#) to "L" and write enable signal W# to"L" at a rising edge of clock signal K.

In the array write cycle, externally applied address signals (missaddresses) Ac and Aa are both taken as the column address signal and therow address signal for the DRAM. In this state, the SRAM array can notbe accessed. In the setting cycle of the array write cycle, execution ofhit write cycle is inhibited even if a hit write occurs. Therefore,cache hit designating signal CH# is set to "H".

Subsequent to the setting cycle of the array write cycle, a hit readcycle is carried out. In the hit read cycle, chip select signal E# andcache hit designating signal CH# are set to "L", and output enablesignal G# is set to "L". In this state, the SRAM array is accessed inaccordance with the address signal Ac, and corresponding data Q5 isoutput. In the example of FIG. 182, cache read is again carried out inthe last cycle of the array write cycle, and cache data Q6 in accordancewith address C6 is output.

In the array write setting cycle, the address Aa is represented as amiss address (Miss Add). It means that the address necessary fortransferring data from the SRAM array to the DRAM array is an addressfrom an externally provided tag memory. FIG. 183 shows operation timingsat a miss write. The miss writing is set by setting chip select signalE# to "L" and write enable signal W# to "L" at a rising edge of clocksignal K. At this time, external addresses Ac and Aa are taken as thecolumn address COL 1 and row address ROW 1 of the DRAM array, andexternally applied write data D1 is taken. In this miss writing, theDRAM and SRAM arrays are accessed, and data D1 is written to acorresponding memory cell of the SRAM array. Writing of data to the SRAMand DRAM arrays may be carried out in accordance with any of the datatransfer methods described above.

When the miss write cycle is completed, the DRAM array enters theprecharge cycle. In the precharge cycle, the SRAM can be accessed. Inthe example of FIG. 183, hit read, hit read and hit write operations arecarried out. In respective operation cycles, the address Ac is taken asSRAM array addresses C2, C3 and C4, respectively, output data Q2 and Q3are output, and write data D4 is written.

Thereafter, the array write cycle is executed. The array write cycle issimilar to that shown in FIG. 182. In the setting cycle of the arraywrite cycle, control signal CC1# (corresponding to the array accessdesignating signal (cache access inhibiting signal) CI#) is set to "L"and access to the SRAM array is inhibited. Therefore, even if a hit readoccurs in the array write setting cycle, this hit reading is not carriedout.

Successive to the setting cycle for the array write cycle, a hit writecycle is carried out. The hit write cycle is set by setting chip selectsignal # to "L" at a rising edge of clock signal K. Since hit reading isdesignated, write enable signal W# is set to "H" and output enablesignal G# is set to "L" in this state. In this state also, the arraywrite cycle is set, external address (Miss Add) is simultaneouslyapplied as addresses Ac and Aa, and these addresses are taken as thecolumn address Col 2 and row address Row 2 of the DRAM array.

A hit write cycle is executed successive to the array write settingcycle, the address Ac is taken as an address C5 for the SRAM, and dataD5 applied at that time is written to the corresponding SRAM memorycell. A hit read cycle is executed in the last cycle of the array writecycle, address Ac is taken as a column address C6 of the SRAM array, andcorresponding data Q6 is output.

FIGS. 184 and 185 show the manner of connection between a memorycontroller and the CDRAM in accordance with the method in which theaddresses are commonly used.

FIG. 184 shows connection between an external control device and theCDRAM in accordance with direct mapping method. The manner of connectionshown in FIG. 184 corresponds to the manner of connection shown in FIG.79. In this manner of connection shown in FIG. 184, 8 bits of addresssignals A6 to A13 are applied to SRAM row decoder 202. 6 bits of addresssignals A6 to A11 of 8 bits of address signals A6 to A13 are applied toDRAM column decoder 103. Address signals A12 and A13 from the CPU and 8bits of address signals A14 to A21 from a selector 672 are applied torow decoder 102 of DRAM 100. In this structure shown in FIG. 184, rowaddress signals and column address signals of the DRAM are applied innon-multiplexed manner. Therefore, a multiplex circuit as shown in FIG.79 is not externally provided. Chip select signal E# and cache hitdesignating signal C# are applied to a clock control circuit 4400, andoperations in accordance with accessing to the SRAM array and to theDRAM array are carried out. Clock control circuit 4400 includes controlclock buffer 250, SRAM array driving circuit 264 and DRAM array drivingcircuit 260 shown in FIG. 32 or 105, and determining circuit 4030 shownin FIG. 180.

Referring to FIG. 184, address signals A6 to A11 are applied to columndecoder 103 for the DRAM array from an output portion of SRAM rowdecoder 202. Signals may be output from predecoder portion as shown inFIG. 179, or, alternatively, SRAM word line selecting signals may beapplied. FIG. 184 simply shows that part of the row address signals ofthe SRAM array and part of column address signals of the DRAM arefunctionally used commonly. FIG. 184 does not exactly reflect the actualmanner of connection.

The structure of external control circuit 650 is the same as that shownin FIG. 79. Compared with FIG. 79, in the structure of FIG. 184,multiplex circuit 705 for multiplexing the row address signals and thecolumn address signals for the DRAM is not necessary, the system sizecan be reduced, and DRAM column addresses can be easily taken.

FIG. 185 shows a manner of connection of addresses when the CDRAM has acache structure of 4 way set associative method. The structure shown inFIG. 185 corresponds to the address connecting structure shown in FIG.170. In the structure of FIG. 185, address signals A6 to A11 from theCPU and way addresses W0 and W1 from a controller 750 are applied toSRAM column decoder 202. Out of address signals applied to SRAM rowdecoder 202, address signals A6 to All are applied to DRAM columndecoder 103. Other structures are the same as those shown in FIG. 80except that multiplex circuit 700 for multiplexing a row address and acolumn address of the DRAM array is not provided. The correspondingportions are denoted by the same reference characters.

In this structure also, even if address signals are commonly used by theSRAM and DRAM, the cache structure can be easily changed.

As described above, by using some of the SRAM address bits as DRAMaddress bits, address non-multiplexing method of the DRAM address can berealized without increasing the number of pin terminals, and columnaddresses for the DRAM array can be easily taken.

[A Further Embodiment of Data Transfer Method]

In a CDRAM, it is preferred to access at high speed even at a cachemiss. A structure for transferring and reading data at high speed evenat a cache miss will be described with reference to FIGS. 186 through193.

Briefly stating, DRAM array have data reading path and data writing pathprovided separately from each other.

FIG. 186 shows a structure which carries out high speed data transfer,high speed data reading even at a cache miss, and increases speed ofoperation of data transfer such as high speed copy back mode. FIG. 186shows structures of portions related to one memory block.

In a DRAM, a data reading path and a data writing path are providedseparately. Accordingly, a global IO line includes global read linepairs GOLa and GOLb for transmitting data read from the DRAM array, andglobal write line pair GILa and GILb for transmitting write data to theDRAM array. The global read line pair GOLa and the global write linepair GILa are arranged parallel to each other, and global read line pairGOLb and the global write line pair GILb are arranged parallel to eachother. The global read line pair GOL (generally represents global readline pairs) and the global write line pair GIL (generically representsglobal write line pairs) correspond to the global IO line pair GIL shownin FIG. 8.

Local read line pair LOLa and LOLb are provided corresponding to theglobal read line pairs GOLa and GOLb. Local write line pairs LILa andLILb are provided corresponding to the global write line pairs GILa andGILb.

A read gate ROGa which turns on in response to a read block selectingsignal φRBA is provided between the global read line pair GOLa and localread line pair LOLa. A read gate ROGb which turns on in response to aread block selecting signal φRBA is provided between global read linepair GOLb and local read line pair LOLb.

A write block selecting gate WIGa which turns on in response to a writeblock selecting signal φWBA is provided between global write line pairGILa and local write line pair LILb. A write block selecting gate WIGbwhich turns on in response to a write block selecting signal φWBA isprovided between global write line pair GILb and local write line pairLILb.

A local transfer gate LTG for transmitting selected memory cell data tolocal read line pair LOL, and a write gate IG for connecting theselected memory cell to local write line pair LIL are provided for eachbit line pair DBL.

A write column selecting line WCSL and a read column selecting line WCSLare provided for setting local transfer gate LTG and write gate IG to aselected state (conductive state). A write column selecting line WCSLand a read column selecting line RCSL constitute a pair and arranged inparallel. A write column selecting signal generated when data is to bewritten from DRAM column decoder is transmitted to write columnselecting line WCSL. A read column selecting line generated when data isto be read from the DRAM array is transmitted to read colunm selectingline RCSL. The write column selecting line WCSL and read columnselecting line RCSL are arranged to select two columns, respectively.This structure corresponds to the column selecting line CSL shown inFIG. 8 divided into a signal line for selecting a column for writing anda signal line for selecting a column for reading.

Local transfer gate LTG includes transistors LTR 3 and LTR 4 fordifferentially amplifying a signal on DRAM bit line pair DBL, andswitching transistors LTR 1 and LTR 2 which turn on in response to asignal potential on read column selecting line RCSL for transmitting thesignal amplified by the transistors LTR 3 and LTR 4 to local read linepair LOL. One terminal of each of the transistors LTR 3 and LTR 4 isconnected to a fixed potential Vss, which is, for example, the groundpotential. In this structure, local transfer gate LTG inverts thepotential on DRAM bit line pair and transmits the same to local readline pair LOL. Transistors LTR 3 and LTR 4 are formed of MOS transistors(insulated gate type field effect transistors), with their gatesconnected to the DRAM bit line pair DBL. Therefore, local transfer gateLTG transmits the signal potential on the DRAM bit line pair DBL at highspeed to local read line pair LOL without any adverse influence to thesignal potential on the DRAM bit line pair DBL.

Write gate IG includes switching transistors IGR 1 and IGR 2 which turnon in response to the signal potential on write column selecting lineWCSL for connecting the DRAM bit line pair to local write line pair LIL.

Other structures in the DRAM array are the same as those shown in FIG.8.

Transfer gates BTGA and BTGB are provided corresponding to two pairs ofglobal write line pair GIL and global read line pairs GOL. Transfer gateBTG (generically represents transfer gates BTGA and BTGB) is connectedto global read line pairs G0L and global write line pairs GIL.Structures of transfer gates BTGA and BTGB will be described in detaillater. Transfer control signals φTSL, φTLD and φTDS are applied totransfer gates BTGA and BTGB.

Control signal φTDS is generated when data is to be transferred from theDRAM array to the SRAM array. Control signal φTSL is generated when datais to be transferred from the SRAM array to the latch in the transfergate BTG. Control signal φTLD is generated when the latched data is tobe written to the DRAM array. Transfer gates BTGA and BTGB, detailedstructure of which will be described later, include latching means forlatching data read from the SRAM array. Data transfer operation betweenthe DRAM array and the SRAM array when the circuit of FIG. 186 is usedwill be described. FIG. 187 is a diagram of signal waveforms showingdata transfer operation from the DRAM to the SRAM in the array structureshown in FIG. 186. The signal waveforms of data transfer operation shownin FIG. 187 correspond to the signal waveforms showing data transferoperation of FIG. 55.

At time t1, equalizing signal φEQ falls to "L" and precharging state inthe DRAM array ends. Then a DRAM word line DWL is selected at t2, andpotential at the selected word line rises.

At time ts1, row selecting operation is being carried out in the SRAMarray, potential of the selected SRAM word line SWL rises to "H", andmemory cell data connected to the selected word line is transmitted toSRAM bit line pair SBL. The signal potential on SRAM bit line pair SBLis transferred to the latching means included in the transfer gate inresponse to transfer designating signal φTSL and latched therein.

In the DRAM, signal potential on the selected word line DWL rises to "H"at time t2, and when signal potential on DRAM bit line pair DBL attainssufficient magnitude, sense amplifier activating signal φSAN attains "L"at time t3 and sense amplifier activating signal /φSAP rises to "H" attime t4. Consequently, signal potentials on DRAM bit line pair DBL areset to "H" and "L" corresponding to the read data, respectively.

Local transfer gate LTG directly receives signal potentials on the DRAMbit line pair DBL.

Before the rise of the sense amplifier activating signal /SAN at timet3, signal potential to read column selecting line RCSL rises to "H".Consequently, small change of the signal potential generated in DRAM bitline pair DBL is amplified at high speed at local transfer gate LTG andis transmitted to local read line pair LOL.

When signal potential on DRAM bit line pair DBL is transmitted to localread line pair LOL, read block selecting signal φRBA rises to "H" attime t7'. Consequently, local read line pair LOL is connected to globalread line pair GOL, and the change in signal potential generated in theDRAM bit line pair DBL is transmitted through global read line pair GOLto transfer gate BTG.

Before the generation of change in signal potential of the global readline pair GOL at time t7', transfer control signal φTDS has beengenerated at time t3. The change in signal potential generated on globalread line pair GOL is transmitted to a corresponding memory cell of theSRAM array at high speed through the transfer gate BTG.

Therefore, by the time the amplifying operation on DRAM bit line pairDBL by DRAM sense amplifier DSA is completed at time t5, data transferto the SRAM array has already been completed.

By such a structure as described above in which a local transfer gate isprovided and DRAM bit line pair DBL is connected to transfer gate BTG,data transfer can be carried out without waiting for completion of senseamplifying operation by DRAM sense amplifier DSA.

Arrows and signal waveforms shown by dotted lines in FIG. 187 showdifferences over data transfer operation shown in FIG. 55. As isapparent from the comparison of the signal waveforms, transfer gate BTGcan be activated (control signal φTDS can be generated) beforeactivation of DRAM sense amplifier DSA, and accordingly data can betransferred at high speed in the structure shown in FIG. 187.

The SRAM array can be accessed immediately after the data transfer fromthe DRAM array. Therefore, the SRAM array can be accessed at high speedeven at a cache miss.

The data transfer operation from the SRAM array to the DRAM array willbe described with reference to FIG. 188 showing operation timingsthereof.

Data transfer from the SRAM array to the DRAM array is carried outthrough global write line pair GIL. In this case, global read line pairGOL and local read line pair LOL are not used.

At time t1, the precharge cycle of the DRAM array is completed. At timet2, a DRAM word line DWL is selected, and potential of the selected wordline rises to "H". At t3 and t4, sense amplifier activating signals φSANand φSAP are rendered active, respectively, and signal potentials atDRAM bit line pair DBL attain to values corresponding to the data of theselected memory cell.

At time t5, a write column selecting line WCSL is selected and signalpotential of the selected write column selecting line WCSL rises to "H".Consequently, a selected write gate IG turns on, and local write linepair LOL is connected to the selected DRAM bit line pair DBL.

At time t6, write block selecting signal φWBA rises to "H".Consequently, local write line pair LIL is connected to global writeline pair GIL, and signal potential on global write line pair GILattains to a value corresponding to the signal potential on local writeline pair LIL.

At time t7, transfer control signal φTLD rises to "H", and data whichhas been latched in transfer gate BTG is transmitted to the selectedDRAM bit line pair DBL through global write line pair GIL and localwrite line pair LIL.

FIG. 189 shows a structure of a portion carrying out data transfer fromthe DRAM array to the SRAM array, of the transfer gate BTG. Referring toFIG. 189, transfer gate BTGR includes transistors Tr500 and Tr501 fordifferentially amplifying signal potentials on global read lines GOL and*GOL; and switching transistors Tr503 and Tr502 responsive to transfercontrol signal φTGS for transferring signal potentials on global readlines GOL and *GOL to SRAM bit lines SBLa and *SBLa. Transistor Tr500has its gate coupled to complementary global read line *GOL. Global readlines GOL and *GOL are coupled to local read lines LOL and *LOL,respectively. In the structure shown in FIG. 189, the read blockselecting gate is omitted for simplification.

In local transfer gate LTG, when the potential on DRAM bit line DBL isat "H", transistor LTR 4 is rendered deeper on, and transistor LTR 3 isrendered shallower on. Thus a large current flows through transistor LTR4. The signal potential on DRAM bit line DBL is inversely transmitted toglobal read line *GOL. The signal potential on DRAM bit line *DBL isinversely transmitted to local read line LOL. Transistors Tr500 andTr501 receive the same potential at their gates, and they constitute acurrent mirror type current source to pass the same current flow to thetransistors LTR4 and LTR3 through the global read lines *GOL and GOL.The current flowing through transistor Tr500 is discharged throughtransistors LTR 2 and LTR 4.

Since a current mirror circuit is formed, the same current as intransistor Tr500 flows in the transistor Tr501. However, sincetransistor LTR 3 is at shallow on state or off state, the signalpotential of global read line GOL is charged to "H" at high speed. Afterthe signal potentials of global read lines GOL and *GOL are sufficientlyamplified to "H" and "L", transfer control signal φTDS rises to "H", andsignal potentials on global read lines GOL and *GOL are transmitted toSRAM bit lines SBL and *SBL, respectively.

In the structure of transfer gate BTGR, transistors Tr500, Tr501, LTR 1,LTR 2, LTR 3 and LTR 4 constitute a current mirror type amplifyingcircuit. Even if the signal potential transmitted to DRAM bit lines DBLand *DBL is small, it can be amplified at high speed, and signalpotentials on global read lines GOL and *GOL attain to (inverted) valuescorresponding to DRAM bit lines *DBL and DBL. By this structure, thepotentials on the DRAM bit lines are amplified by the current mirrortype amplifying circuit having DRAM bit lines *DBL and DBL as directinputs and are transmitted to SRAM bit line pair SBLa, *SBLa. Thus datacan be transferred at high speed from the DRAM array to the SRAM array.

FIG. 190 shows a structure of the transfer gate shown in FIG. 186 fortransferring data from the SRAM array to the DRAM array. The structureof data transfer gate BTGW shown in FIG. 190 corresponds to a structureof data transfer circuit shown in FIG. 51 with amplifying circuitportion omitted.

Referring to FIG. 190, data transfer gate BTGW includes a transmissiongate 5103 responsive to transfer control signal φTSL for inverting andtransmitting data on SRAM bit lines SBLa and *SBLa; a latch circuit 5100for latching data of SRAM bit lines SBLa and *SBLa which have beentransmitted from transmission gate 5103; and transmission gates 5102aand 5102b responsive to transfer control signal φTLD for transmittingdata latched in latch circuit 5100 to global write lines GIL and *GIL,respectively.

Transfer gate BTGW further includes a gate circuit 5101b responsive toan array write designating signal AWDE and a DRAM column decoder output(which is also a SRAM column decoder output) SAY for connecting internalwrite data line *DBW to global write line *GIL; and a gate circuit 5101aresponsive to the array write designating signal AWDE and column decoderoutput SAY for connecting internal write data line DBW to global writeline GIL. When the DRAM array is directly accessed, write data istransmitted through gate circuits 5101a and 5101b to the DRAM array.

Transfer gate BTGW further includes gate circuits 5104a and 5104bresponsive to a write designating signal SWDE to the SRAM and to SRAMcolumn decoder output (which is also a column selecting signal of theDRAM array) SAY for connecting external write data lines DBW and *DBW toSRAM bit lines SBLa and *SBLa. The structure of transfer gate BTGW shownin FIG. 190 is the same as that of the portion for transferring datafrom SRAM array to the DRAM array in the transfer gate shown in FIG. 57,and therefore detailed description thereof is not repeated.

FIG. 191 shows a circuit structure for driving write column selectingsignal line WCSL and read column selecting signal line RCSL. Referringto FIG. 191, a signal driving circuit 5110 is provided with respect to acolumn selecting line CSL from DRAM column decoder 103. Signal linedriving circuit 5110 includes a gate circuit 5111 receiving a columnselecting signal CSL from DRAM column decoder 103 and an internal writeenable signal *W, and a gate circuit 5112 receiving column selectingsignal CSL, sense completion signal SC and internal write enable signalW. A signal for driving read column selecting line RCSL is output fromgate circuit 5111. A signal for driving write column selecting line WCSLis output from gate circuit 5112.

Internal write enable signals *W and W may be taken inside insynchronization with clock K in response to an externally appliedcontrol signal W#. The internal write enable signal W may be generatedat the same timing as the array write designating signal AWDE. Sensecompletion signal SC indicates completion of sensing operation of senseamplifier DSA in the DRAM array, which is generated by providing aprescribed delay to sense driving signal SANE or φSAPE. In this manner,a structure in which read column selecting line RCSL is selected whendata is to be written to the DRAM, and write column selecting line WCSLis selected when data is to be written from DRAM array can be provided.

FIG. 192 shows a structure for generating block selecting signals φRBAand φWBA. The circuit for generating read block selecting signal φRBAincludes a delay circuit 5120 providing a prescribed time delay to readcolumn selecting signal RCSL, and a gate circuit 5121 receiving anoutput from delay circuit 5120 and block selecting signal φBA (see FIG.8). Read block selecting signal 100 RBA is output from gate circuit5121.

The circuit for generating write block selecting signal φWBA includes adelay circuit 5130 for providing a prescribed delay to write columnselecting signal WCSL, and a gate circuit 5131 receiving an output fromdelay circuit 5130 and block selecting signal φBA. Gate circuit 5131generates write block selecting signal φWBA. Gate circuits 5121 and 5131generate signals at "H" when both inputs thereof are at "H".

In the above described structure in which data writing path and readingpath are separately provided in the DRAM array, data must be transferredfrom the DRAM array to the SRAM array as fast as possible. Therefore, itis preferred to drive block selecting signal φRBA and read columnselecting line RCSL at a timing as fast as possible. The structure ofFIGS. 176 and 177 in which address signals of the DRAM array and theSRAM array are commonly used is most effective for this structure. Bythis structure, the row address signal and the column address signal forthe DRAM array can be applied in the non-multiplexed manner, read columnselecting line RCSL can be generated immediately after the selection ofthe word line DWL in the DRAM array to render conductive the localtransfer gate, and the DRAM bit line pair can be coupled at an earliertiming to the transfer gate BTG through local read line pair LOL andglobal read line pair GOL.

FIG. 193 shows a structure of a decoder circuit when the non-multiplexedaddress method structure is applied to the separated IO structure of theDRAM array. Referring to FIG. 193, SRAM column decoder 5141 receivesapplied address signals Ac0 to Ac3, decodes the same and generate acolumn selecting signal SAY. Column selecting signal SAY is used as acolumn selecting signal of the SRAM array as well as a column selectingsignal of the DRAM array. SRAM row decoder 5142 receives address signalsAc4 to Ac11 and generates a signal for driving SRAM word line SWL. DRAMcolumn selecting circuit 5143 receives address signals Ac6 to Ac11 outof applied address signals Ac4 to Ac11 and generates a signal fordriving write column selecting line WCSL and read column selecting lineRCSL. DRAM row selecting circuit 5144 receives address signals Aa0 toAa9 and generates a block selecting signal φBA and DRAM word linedriving signal DWL. In the structure shown in FIG. 193, address signalsAc0 to Acll and Aa0 to Aa9 can be simultaneously applied, read columnselecting line RCSL can be driven at high speed, and data can betransferred from the DRAM array to the SRAM array at higher speed moreeffectively.

In the structure shown in FIG. 186, local read line pair LOL and localwrite line pair LIL are arranged on both ends of the bit line pair DBL.However, the local read line pair LOL and local write line pair LIL maybe arranged on one side (for example a side near the transfer gate BTG)of the bit line pair DBL, or they may be arranged at the center of thebit line pair DBL.

By the above described structure, by utilizing high speed copy backmethod even at a cache miss, precharging and copy back operation of theDRAM array can be executed on the back ground of a cache hit, andtherefore, the performance of the CDRAM can be significantly improved,by reducing access time at a cache miss.

By the structure for separating data reading path and data writing pathof the DRAM array combined with the structure for applying addresses innon-multiplexed manner and with high speed copy back mode, remarkableeffect can be obtained.

[Modification of Separated IO Array Architecture CDRAM]

In this section, a modification of the array arrangement shown in FIG.186 is described, with reference to FIGS. 194 through 196. The modifiedarray arrangement can be considered as a combination of the clampingarchitecture shown in FIG. 61 and the separated IO DRAM arrayarchitecture shown in FIG. 186. Clamping circuit is provided for globalwrite line pair GIL.

FIG. 194 shows a main portion of another CDRAM which is a modificationof CDRAM of FIG. 186. In FIG. 194, the components corresponding to thoseof FIG. 186 have like reference numerals, and characters, and nodetailed explanation thereon is developed for saving duplicatedescription.

Referring to FIG. 194, SRAM bit line pair SBL is provided with aclamping circuit CRS. The clamping circuit CRS has the same constructionas that shown in FIG. 62 or FIG. 70. SRAM clamping circuit CRS has theclamping operation inhibited by an inversion /DTS of the data transfercontrol signal DTS instructing data transfer from DRAM array to SRAMarray.

Global write line pair GIL (GILa, GILb) is provided with a clampingcircuit CRDW for clamping the potentials of the global write lines. DRAMclamping circuit CRDW has the clamping operation inhibited by aninversion /DTA of the data transfer control signal DTA instructing datatransfer to DRAM array. DRAM clamping circuit CRDW may be provided forthe local write line pair LIL, (LILa, LILb), and may be provided forboth the global write line pair GIL and the local write line pair LIL.

Bidirectional transfer gate BIG carries out data transfer between SRAMarray and DRAM array in response to the data transfer control signalsDTA, DTS and DTL. The transfer gate BTG has its same construction asthat shown in FIGS. 189 and 190. The signal DTA corresponds to thesignal φTLD and allows data transfer from the latch circuit to DRAMarray. The signal DTS corresponds to the signal φTDS and allows datatransfer from DRAM array to SRAM array. The signal DTL corresponds tothe signal φTSL and allows data transfer from SRAM array to the latchcircuit.

Now, data transfer operation of the modified, separated IO configurationCDRAM will be described briefly with reference to FIGS. 189, 190 and194. The operation of the bidirectional transfer gate is the same asthat of the gate shown in FIGS. 189 and 190.

With the real out gate of FIG. 189, the signal potentials on a selectedDRAM bit line pair DBL can be transferred to SRAM array at a high speedwithout adverse effect on the selected DRAM bit line DBL when a minutepotential difference is produced in the DRAM bit line pair DBL.Consequently, data can be transferred from DRAM array to SRAM array at ahigh speed.

In this operation, if SRAM clamping circuit CRS is in an operating statefor carrying out the clamping operation, the clamping current flowsthrough the transistor Tr502 or Tr503 into the local transfer gate LTG,in which the current is discharged through the transistor LTR3 or LTR4(see FIG. 189). In order to prevent the current flow supplied from theclamping circuit CRS from flowing into the local read out gate LTG, theclamping operation of SRAM clamping circuit CRS is inhibited during theperiod when the transfer control signal DTS is active, to provide areduced current consumption during data transfer to SRAM array.

Meanwhile, in data transfer to DRAM array, the clamping current fromDRAM clamping circuit CRDW flows through the gate circuit 1812 and thedischarging transistors in the inverter circuit of the latch circuit1811 to the ground. Thus, in this data transfer operation, DRAM clampingcircuit CRDW has the clamping operation inhibited in response to thesignal DTA.

FIGS. 195 and 196 are operating waveform diagrams showing data transferoperations from DRAM to SRAM and from SRAM to DRAM, respectively. Theoperations shown in FIGS. 195 and 196 are the same as those shown inFIGS. 187 and 188 except the precharge level of global read line pairGOL, local read line pair GIL, global write line pair GIL, local writeline pair LIL and SRAM bit line pair SBL. For precharging the globalread line pair GIL and local read line pair LIL at "H", there may beadditionally provided clamping transistors for clamping the potentialsof these signal lines. For example, clamping transistors may be providedin parallel with the transistors Tr500 and Tr501 in the readingbidirectional transfer gate BTGR. In the following, only the operationsrelated to inhibition of the clamping are described with reference toFIGS. 195 and 196.

In FIG. 195, the transfer control signal DTS is generated at the time t3prior to the time t7' at which the signal potential change is caused onthe global read line pair GOL. The signal change on the global read linepair GOL is transferred to a selected SRAM memory cell at a high speed.If SRAM clamping circuit CRS is operating, the clamping transistors SQ70and SQ80 in the clamping circuit CRS supply a current flow charging theglobal read line pair and flowing into the local transfer gate LTG,before the global read line pair GOL has the signal potentials changedaccording to read out DRAM cell data. SRAM bit line clamping circuit CRSis inhibited from clamping SRAM bit lines in response to the transfercontrol signal DTS. Thus, SRAM bit line pair is charged and dischargedby the current mirror circuit (transistors Tr500 and Tr501) in thebidirectional transfer gate BTG, to have the potential levelscorresponding to data read out from the selected DRAM cell.

As described above, inhibition of the clamping of SRAM clamping circuitCRS in response to the data transfer control signal DTS implements fastand reliable data transfer with less current consumption without adverseeffect on the amplifying operation of local transfer gate LTG.

Now, in FIG. 196, local write line pair LIL and global read line pairGOL are shown precharged or pulled up to "H" of Vcc-Vth by DRAM clampingcircuit CRDW. Data transfer operation from SRAM to DRAM or from thelatch circuit to DRAM will be described. In this description, only theoperations to the clamping are described because of the similarity ofthe operation to that of FIG. 188.

At the time t5, a write column selection line WCSL is selected, and thepotential thereof rises to "H". Responsively, a write gate IG turns onto connect the local write line pair LIL to the selected DRAM bit linepair DBL. The write gate IG has a relatively large resistance. Thus,DRAM bit line pair has the potentials of full swing to "H" of Vcc and"L" of Vss, while the local write line pair LIL has "L" level potentialraised from Vss due to the clamping of DRAM clamping circuit CRDW.

At the time t6, the write block selection signal φWBA rises to "H".Consequently, the local write line pair LIL is connected with the globalwrite line pair GIL to have the potentials corresponding to the signalpotential levels of the local write line pair LIL. If the gate WIG has asufficiently larger resistance than the gate IG has, the global writeline pair GIL has "L" level potential higher than "L" level potential ofthe local write line pair LIL (in the case where a clamping circuit isprovided only for the global write line pair).

At the time t7, the transfer control signal DTA rises to "H", and datalatched in the bidirectional transfer gate BTG is transferred to theselected DRAM bit line pair DBL through the global write line pair GILand local write line pair LIL.

The clamping circuit CRDW for the write line pair GIL (and LIL asnecessary) has the clamping operation inhibited. Consequently, the pathof current flow from the clamping circuit CRDW into the dischargingtransistor in the inverter circuit of the bidirectional transfer gate iscut off to reduce the current consumption in this data transferoperation. The local write line pair LIL and the global write line pairGIL have the potential levels of "H" and "L" corresponding to the signalpotentials latched in the latch circuit 1811.

As described above, the clamping circuit provided at data receiving sidebus has the clamping operation inhibited or deactivated, and thereforeno penetrating current flows into a discharging transistor in thebidirectional transfer gate BTG to significantly reduce the currentconsumption even in the separated IO DRAM array type CDRAM.

The global write line pair GIL and the local write line pair LIL may beprecharged to an intermediate potential of Vcc/2 by a clamping circuit.

The controlled clamping operation can be applied to a semiconductormemory device other than CDRAM of the invention as far as thesemiconductor memory device includes SRAM array, DRAM array and a datatransfer gate for data transfer between DRAM array and SRAM array.

[Other Function: Burst Mode]

Connection with external operational processing unit (CPU) having burstmode function will be described with reference to FIGS. 197 through 201.

In the burst mode, a first address is set in an address counter, andsubsequent address are generated sequentially from the counter duringthe burst mode operation or by a predetermined number of times.

As described previously, burst mode is an operation mode in which a datablock are transferred at one time from the CPU. Control of the burstmode function is supported by a circuit portion of the additionalfunction control circuit 299 shown in FIG. 32.

FIG. 197 shows a circuit portion for realizing burst mode operation.Referring to FIG. 197, burst mode control system includes a BE buffercircuit 6001 taking an externally applied burst enable signal BE# inresponse to internal clock signal int. K for generating an internalburst enable signal /BE; a one shot pulse generating circuit 6002responsive to the first internal burst enable signal /BE from BE buffercircuit 6001 for generating a one shot pulse signal φBE having aprescribed pulse width; and a gate circuit 6003 responsive to the oneshot pulse signal φBE having a prescribed pulse width; and a gatecircuit 6003 responsive to one shot pulse signal φBE for gating theinternal clock int. K. When one shot pulse signal φBE is generated, gatecircuit 6003 inhibits passage of internal clock int. K. One shot pulsegenerating circuit 6002 does not respond to the second and the following/BE signals. When burst transfer operation is completed, the circuit6003 is reset. This resetting is realized by providing a timer and byprohibiting generation of pulses while the timer is operating.

Burst enable control circuitry further includes an address counter 6004for counting internal clock signals int. K applied from gate circuit6003 with the initial value thereof set at internal address signal int.Ac applied from an address buffer (see FIG. 32); and a multiplexercircuit 6007 for selectively passing either the count value of addresscounter 6004 or internal address signal int. Ac. An output frommultiplexer circuit 6007 is transmitted to the SRAM row decoder and thecolumn decoder. Address counter 6004 and multiplexer circuit 6007 aredifferent from the address counter for generating refresh addresses forthe refreshing operation and the multiplexer circuit for switching therefresh address and the DRAM address.

The burst enable control circuitry further includes a burst data numberstoring circuit 6006 for storing the number of data to be transferred inthe burst mode and a down counter 6005 for counting down the internalclock signals int. K with the initial count value being the burst datanumber stored in burst data number storing circuit 6006. Down counter6005 starts its counting operation when internal burst enable signal /BEis generated from BE buffer 6001. Down counter 6005 switches connectionpath of multiplexer circuit 6007 in accordance with the count value atthat time.

Down counter 6005 is reset when internal burst enable signal /BE isinactive at a rising edge of internal clock signal int. K. When internalburst enable signal /BE is active (at "L" level) at a rising edge ofinternal clock signal int. K, it carries out counting operation. Downcounter 6005 controls connection path of multiplexer circuit 6007 suchthat an output from address counter 6004 is selected during countingoperation. Down counter 6005 is reset when the number of burst datastored in the burst data number storing circuit 6006 is counted andswitches connection path of multiplexer circuit 6007 such that internaladdress signal int. Ac from the address buffer is selected. Theoperation of the structure shown in FIG. 197 will be described withreference to FIG. 198 which is a diagram of signal waveforms.

In normal accessing to SRAM array, chip select signal E# is set to "L"and burst enable signal BE# is set to "" at a rising edge of externalclock signal K.

In this state, internal burst enable signal /BE is also at "H", andpulse signal is not generated from one shot pulse generating circuit6002. Down counter circuit 6005 is also kept at the reset state. In thisstate, multiplexer circuit 6007 selects internal address signal int. Ac(cache address) applied from the address buffer and transmits the sameto the SRAM row decoder and the column decoder. A part of the addresssignal may be applied to the DRAM column decoder.

Consequently, the SRAM array is accessed in accordance with the addressAc1 for the SRAM applied at the rising edge of external clock signal K,and data Q1 corresponding to this address Ac1 is output.

When chip select signal E#, cache hit designating signal CH# and burstenable signal BE# are set to "L" at a rising edge of external clocksignal K, the burst mode is effected. In this state, a one shot pulsesignal φBE is generated in response to a rise of internal burst enablesignal /BE from one shot pulse generating circuit 6002. In response toone shot pulse signal φBE, address counter 6004 takes internal addresssignal int. Ac (Ac2) applied from the address buffer as a count initialvalue, and applies the initial value to multiplexer circuit 6007. Whenthe one shot pulse signal φBE is generated, gate circuit 6003 inhibitstransmission of internal clock signal into K. Therefore, in this clockcycle, the address signal Ac applied at a rising edge of clock signal Kis applied from address counter 6004 to multiplexer circuit 6007.

Down counter 6005 is activated in response to an active state ("L") ofinternal burst enable signal /BE, and carries out counting-downoperation starting at the value stored in burst data number storingcircuit 6006. During the counting operation, down counter 6005 generatesa signal indicating that the operation is in the burst mode tomultiplexer circuit 6007. Multiplexer circuit 6007 selects an outputfrom address counter 6004 in response to the burst mode designatingsignal from down counter 6005, and applies the output to the SRAM rowdecoder and the SRAM column decoder. The SRAM array is accessed inaccordance with this address Ac2, and corresponding data Q2 is output.

Thereafter, when chip select signal E#, cache hit signal CH# and burstenable signal BE# are set to "L" at a rising edge of external clocksignal K, externally applied address signal Ac is neglected, and accessto the SRAM array is carried out in accordance with address counter6004. Namely, internal clock signal int. K is applied to address counter6004 through gate circuit 6003. Address counter 6004 carries outcounting operation in accordance with the internal clock signal (countup or count down), and applies the count value to multiplexer circuit6007.

Multiplexer circuit 6007 selects the count value of address counter 6004in accordance with a control signal from down counter 6005 and appliesthe count to the SRAM row decoder and the SRAM column decoder.Therefore, in the burst mode, access in accordance with the count valuefrom address counter 6004 is effected, and corresponding data Q3, . . .are output every clock cycle. The burst mode operation ends when burstmode enable signal BE# is set to "H" at a rising edge of external clocksignal K, or when counting down operation of down counter 6005 iscompleted.

The burst data number information stored in the burst data numberstoring circuit 6006 may be fixedly programmed in advance, or it may bestored in a command register or the like at each burst transfer mode.

In the structure shown in FIG. 197, gate circuit 6003 inhibitstransmission of internal clock signal int. K in accordance with one shotpulse signal φBE. Alternatively, a structure in which address counter6004 sets internal address int. Ac as a count initial value wheninternal clock signal int. K and one shot pulse signal φBE are appliedmay be used, without using gate circuit 6003.

FIG. 199 shows one example of a specific structure of the addresscounter circuit. Referring to FIG. 199, address counter 6004 includes ncascade connected in array counter circuits BCC 1 to BCC n. Binarycounter circuits BCC 1 to BCC n are asynchronous type counter circuitsand internal clock signal int. K is applied only to the leastsignificant binary counter circuit BCC 1. Each binary counter circuiteffects binary counting operation, and output carrier signals CK0 toCKn-1 when count value reaches "1". The carry outputs CK0 to CKn-1 areapplied to clock inputs of binary counter circuits BCC 2 to BCC n of thesucceeding stages, respectively. Complementary count values A0, *A0 toAn and *An-1 are generated from binary counter circuits BCC 1 to BCC n.Address counter 6004 further includes an up/down switching circuit 6010for determining whether count up operation or count down operation is tobe executed. Up/down switching circuit 6010 selectively passes eitherthe outputs A0 to An or complementary outputs *A0 to An-1 from countercircuits BCC 1 to BCC n in response to an up/down setting signal φUD.When count up operation is set, up/down switching circuit 6010 selectscounter outputs A0 to An. If count down operation is set, up/downswitching circuit 6010 selects complementary outputs *A0 to *An-1.Up/down setting signal φUD may be a control signal set in a commandregister, or it may be a control signal for setting one of the countingoperation fixedly by wiring or the like.

The structure of the counter circuit is not limited to that of FIG. 199.Any counter circuit having a function for setting an initial value maybe used.

FIG. 200 shows an example of a specific structure of burst data numberstoring circuit 6006. In the structure shown in FIG. 200, a commandregister is used as burst data number storing circuit 6006. Burst datanumber storing circuit 6006 includes a switching transistor Tr600responsive to a control signal φCR for transmitting data DQ applied todata input/output pin terminal; and inverter circuits V600, V601 andV602 for latching data applied through switching transistor Tr600.Inverter circuits V600 and V601 constitute a latch circuit.

Control signal φCR is a control signal generated in the command registersetting mode. Combination of control signals (command registerdesignating signals Ar, Ar1 and W#) is determined dependent on thecommand register used for storing the burst data number.

In the structure shown in FIG. 200, the burst data number information isshown to be applied through data input/output terminal DQ. However, itmay be applied through a data input terminal D.

The burst data number information may be stored in a register used forthat purpose only, not in a command register.

[Application of Burst Mode Function to Other Memory Devices]

FIG. 201 shows a structure of another semiconductor memory having burstmode function. Referring to FIG. 201, the semiconductor memory device6700 includes a memory array 6701 including memory cells arranged inrows and columns, a row decoder 6702 for selecting a row of memory array6701, and a column decoder 6703 for selecting a column of memory array6701.

Semiconductor memory device 6700 further includes an address buffercircuit 6704 receiving an externally applied address ADD for generatingan internal address; an address count circuit 6705 using an output fromaddress buffer circuit 6704 as a count initial value for counting theclock signals from a clock control circuit 6706; and a multiplexercircuit 6707 responsive to a control signal BE from clock controlcircuit 6706 for passing either an output from address count circuit6705 or an output from address buffer circuit 6704. Row and columnaddress signals are applied from multiplexer circuit 6707 to row decoder6702 and column decoder 6703, respectively. Address count circuit 6705includes the structure of address counter 6004, down counter 6005 andburst data number storing circuit 6006 shown in FIG. 197.

Clock control circuit 6706 receives externally applied chip selectsignal /CS, write enable signal /W, output enable signal /OE and burstmode requesting signal BE and generates respective internal controlsignals.

The semiconductor memory device 6700 is supposed to be a static typesemiconductor memory device or a non-multiplexed address type memorydevice. However, a dynamic type semiconductor memory device having highspeed operation mode such as static column mode or page mode may beused. The structures of address count circuit 6705 and multiplexercircuit 6707 are the same as those described above, and therefore thestructures thereof are not shown.

As described above, by providing address count circuit 6705 forgenerating addresses in the burst mode, it becomes not necessary toexternally connect an address generating circuit for the burst mode tothe memory device, and therefore system size can be reduced. Inaddition, wires for connecting the burst mode address counter providedexternally to the semiconductor memory device become unnecessary, signaldelay in the signal lines for connection and current consumptionassociated with charging/discharging of the connecting wires can bereduced. In addition, since the address circuit for the burst mode isprovided in the semiconductor memory device, connection to the CPUhaving burst mode function can be readily realized.

In the structure shown in FIG. 197, an internal address from the addressbuffer is pre-set as the initial count value in the address counter6004. However, the initial count value of address counter 6004 may beset in the command register.

The semiconductor memory device shown in FIG. 201 may be replaced byother semiconductor memory device containing a cache.

[Other Function: Sleep Mode]

An operation mode for reducing current consumption in standby state,that is, a sleep mode will be described with reference to FIGS. 202through 214.

In sleep mode operation, internal clock K is inhibited from beinggenerated. If no internal clock K is generated, self refreshing isresponsively carried out. The function of the sleep mode is realized bythe additional function control circuit 299 shown in FIG. 32.

As described previously and repeatedly, the CDRAM of the presentinvention takes address signals, external control signals and write datain synchronization with the external clock signal K. Therefore, even inthe standby mode, current is consumed in the buffer receiving theseexternal signals.

FIG. 202 shows a structure of a portion related to 1 bit of the addressbuffer (252in; FIG. 32: FIG. 105, 360). Referring to FIG. 202, addressbuffer 7001 includes a clocked inverter 7011 responsive to internalclock signal int. K for inverting and passing applied data; andinverters 7013 and 7014 for latching an output from clocked inverter7011. Clocked inverter 7011 receives internal clock signal int. Kthrough inverter 7012 at its positive control input, and receivesinternal clock signal int. K at its complementary control input.

Clocked inverter 7014 receives chip select signal E through inverter7015 at its positive control input, and receives chip select signal E atits complementary control input.

Inverter 7013 and clocked inverter 7014 are connected in anti-parallel(or cross coupled) to form a latch circuit.

In the structure shown in FIG. 202, clocked inverter 7011 is set to anoutput high impedance state in response to a rise of internal clocksignal int. K. Clocked inverter 7014 functions as an inverter inresponse to a fall of chip select signal E. In this state, in responseto the fall of chip select signal E, a latch circuit is provided byinverter 7013 and clocked inverter 7014. Internal address signal int. Ais generated from inverter 7013.

More specifically, at a rising edge of external clock signal K, externaladdress A which has been applied at that time is latched by the latchcircuit formed of inverter 7013 and clocked inverter 7014, and internaladdress int. A is generated.

As shown in FIG. 202, even if the chip select signal E is at "H" and thechip is in the non-selected state, internal clock signal int. K iscontinuously applied. Therefore, in the standby state, clocked inverter7011 operates and consumes current.

FIG. 203 shows a structure of a clock buffer circuit included in thecontrol clock buffer. FIG. 203 shows a buffer related to chip selectsignal E# as an example. Referring to FIG. 203, buffer circuit 7021includes a p channel MOS transistor Tr700 receiving internal clocksignal int. K at its gate; a p channel MOS transistor Tr701 receivingexternal chip select signal E# at its gate; an n channel MOS transistorTr702 receiving external chip select signal E# at its gate; and an nchannel MOS transistor Tr703 receiving an inverted signal /int. K ofinternal clock signal at its gate. Transistor Tr700 to Tr703 areconnected in series between supply potential Vcc and the other supplypotential (ground potential) Vss. In the structure shown in FIG. 203,the buffer circuit 7021 is set to the output high impedance state at arising edge of external clock signal int. K, and its output portion isset to a floating state at the signal potential which has been appliedthereto. An inverter circuit or a latch circuit may be provided in thenext stage of the buffer circuit having the above described structure.

As shown in FIG. 203, also in the control clock buffer, information istransmitted to the output portion thereof in response to internal clocksignal int. K, and consequently, current is consumed even in the standbymode. In view of the foregoing, a structure for reducing currentconsumption in the standby state will be described in the following.

FIG. 204 is a diagram of signal waveforms showing the sleep modeoperation. The sleep mode is set not synchronized with the externalclock signal K. The sleep mode is set by command register setting signalCRY. More specifically, when control signal CR# falls to generation ofinternal clock signal int. K is stopped. Consequently, operations ofrespective buffer circuits are stopped in the standby state, forexample. A circuit structure for realizing the sleep mode will bedescribed.

FIG. 205 is a block diagram functionally showing the circuit structurefor realizing the sleep mode. Referring to FIG. 205, a sleep modecontrol system includes a sleep control circuit 7052 responsive tocontrol signal CR# for generating a sleep mode control signal SLEEP; andan internal clock generating circuit 7051 responsive to sleep modecontrol signal SLEEP from sleep control circuit 7052 for controllinggeneration/stoppage of internal clock signal int. K. Internal clockgenerating circuit 7051 corresponds to clock buffer 254 shown in FIGS.32 and 105. Sleep control circuit 7052 may be included in additionalfunction control circuit 299 shown in FIG. 32, or a command register maybe used.

FIG. 206 shows an example of a specific structure of internal clockgenerating circuit 7051 shown in FIG. 205. Referring to FIG. 206,internal clock generating circuit 7051 includes an inverter circuit 7061receiving sleep mode control signal SLEEP; an NAND circuit 7062receiving external clock signal K and an output from inverter circuit7061; and an inverter circuit 7063 receiving an output from NAND circuit7062. Sleep mode control signal SLEEP is set to "H" when sleep mode isset. The NAND circuit 7062 functions as an inverter when the output frominverter circuit 7061 is at "H". When the output from inverter circuit7061 is at "L" level, the output of NAND circuit 7062 is fixed to the"H" level.

Therefore, in the structure shown in FIG. 206, generation and stoppageof internal clock signal K can be controlled by sleep mode controlsignal SLEEP.

FIG. 207 shows an example of a specific structure of sleep controlcircuit 7052 generating the sleep mode control signal.

Referring to FIG. 207, sleep control circuit 7052 includes a gatecircuit (NOR circuit) 7501 receiving external command register settingsignal CR# and an output from inverter circuit 7507; an inverter circuit7502A receiving an output from gate circuit 7501; an inverter circuit7502B receiving an output from inverter circuit 7502A; and a gatecircuit (NAND circuit) 7503 receiving an output from inverter circuit7502B and an output from gate circuit (NAND circuit) 7506.

Sleep control circuit 7052 further includes an inverter circuit 7504receiving external command register setting signal CRY; a gate circuit(NAND circuit) 7505 receiving an output from inverter circuit 7504 andexternal control signals Ar0, Ar1 and W#; a gate circuit 7506 receivingboth outputs from NAND circuits 7503 and 7505; an inverter circuit 7507receiving an output from gate circuit 7506; and an inverter circuit 7508receiving an output from inverter circuit 7507. Sleep mode controlsignal SLEEP is generated from inverter circuit 7508.

A CR# buffer 7600 is further shown in FIG. 207. CR# buffer 7600 isincluded in the control clock buffer (see reference numeral 250 in FIG.33). CR# buffer 7600 takes the external command register setting signalCR# in response to internal clock signal int. K and generates internalcontrol signal CR.

The operation of sleep control signal 7052 shown in FIG. 207 will bedescribed with reference to FIG. 208 which is a diagram of signalwaveforms.

Signals CR#, Ar0, Ar1 and W# shown in FIG. 207 are all external controlsignals. Therefore, sleep control circuit 7052 operates asynchronouslywith a clock signal K.

When external command register setting signal CR# is at "H", an outputfrom gate circuit 7501 is "L". Therefore, an output from invertercircuit 7502B is at "L".

Meanwhile, an output from inverter circuit 7504 is "L". Therefore, anoutput from gate circuit 7505 attains "H" regardless of the states ofcontrol signals At0, Ar1 and W#. Gate circuit 7506 receives signals at"H" at both inputs thereof. Consequently, an output from gate circuit7506 attains "L", and sleep mode control signal SLEEP attains "L".

When sleep mode is to be set, external command register setting signalCR# is set to "L". Control signals At0, Ar1 and W# are also set to "H".In this state, gate circuit 7505 receives signals at "H" at its allinputs, and therefore it outputs a signal at "L". Since a signal at "L"is applied to one input of gate circuit 7506, it outputs a signal at"H", and hence sleep mode control signal SLEEP rises to "H".

When sleep mode control signal SLEEP attains "H", an output frominverter circuit 7507 attains "L". Consequently, both inputs of gatecircuit 7501 are at "L", providing an output of "H". Consequently, bothinputs of gate circuit 7503 attain "H" level, providing an output of

In this state, a signal at "L" is applied from gate circuit 7503 to oneinput of gate circuit 7506, and therefore an output from gate circuit7506 attains to regardless of the states of external control signalsAt0, Ar1 and W#.

When external command register setting signal CR# rises to "H" at thisstate, sleep mode control signal SLEEP falls to "L", and thus sleep modeis canceled. When generation of internal clock signal int. K is stoppedby the sleep mode, external refresh designating signal REF# can not betaken at a rising edge of internal clock signal int. K. Therefore,auto-refreshing operation can not be executed. Therefore, in the sleepmode period, self refresh must be carried out instead of auto refresh. Acircuit structure for carrying self refreshing in the sleep mode isshown in FIG. 209.

Referring to FIG. 209, in order to switch auto/self refresh modesdependent on execution of the sleep mode, a self refresh switchingcircuit 7401 is provided. Self refresh switching circuit 7401 monitorsgeneration of internal clock signal int. K and when generation ofinternal clock int. K is stopped, it generates a self refresh switchingsignal Self.

A refresh timer 7402 is activated in response to self refresh switchingsignal Self, and generates a refresh requesting signal /REFREQ at aprescribed interval and applies the same to clock generator 7403. Clockgenerator 7403 receives external clock signal K, external refreshdesignating signal REF# and refresh requesting signal REFREQ fromrefresh timer 7402, determines as to whether refreshing is to beexecuted, and generates various control signals necessary for executingrefreshing. A structure shown in FIG. 163 may be used for the clockgenerator 7403. Functions carried out by clock generator 7403 are thesame as those shown in FIG. 163. Function of switching input and outputis not shown.

Self refresh switching circuit 7401 carries out counting operation inresponse to a rise of internal clock signal int. K, and when internalclock signal int. K is not applied in a prescribed period (for example 1clock cycle), its generates self refresh switching signal Self. Selfrefresh switching circuit 7401 is reset in response to a rise ofinternal clock signal int. K, and sets self refresh switching signalSelf to auto refresh designating state. Refresh timer 7402 is the sameas that shown in FIG. 162 which generates refresh requesting signal/REFREQ at a prescribed interval in response to self refresh switchingsignal Self.

Clock generator 7403 takes external refresh designating signal REF# at arising edge of external clock signal K, and when either refreshdesignating signal RE# or refresh requesting signal /REFREQ is at activestate, carries out necessary operations for refreshing. Internal controlsignals /RAS and /CAS generated from clock generator 7403 are controlsignals for controlling decoding operation and the like for the DRAMarray. Refresh address counter 7407 corresponds to refresh addresscounter shown in FIG. 32 and the like.

In correspondence with the structure shown in FIG. 32, clock generator7403 includes auto-refresh mode detecting circuit 291 and refreshcontrol circuit 292.

FIG. 210 shows a structure of a circuit generating refresh signal REF.The structure shown in FIG. 210 is included in clock generator 7403shown in FIG. 209. Referring to FIG. 210, the circuit for generatingrefresh signal REF includes a REF buffer 7440 responsive to internalclock signal int. K for latching external refresh designating signalREF#; and a gate circuit 7450 receiving an output from REF buffer 7440and refresh requesting signal /REFREQ from refresh timer 7402. Gatecircuit 7450 outputs a signal at "H" when one input thereof attains to"L". When refresh signal REF attains "H", refreshing is carried out.

FIG. 211 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 209. Switching operation between auto refresh/selfrefresh in the sleep mode will be described with reference to FIGS. 209to 211.

At time t1, the sleep mode is set and generation of internal clocksignal int. K is stopped. Self refresh switching circuit 7401 startscounting operation from time t1, and after a prescribed time period,generates self refresh switching signal Self at time t2 and applies thesame to refresh timer 7402. Refresh timer 7402 generates refreshrequesting signal /REFREQ in response to self refresh switching signalSelf and applies the same to clock generator 7403.

Clock generator 7403 generates refresh signal REF in response to refreshrequesting signal /REFREQ and generates internal control signal /RAS. Atthis time, generation of internal control signal /CAS is stopped. Inresponse to internal control signal /RAS, row selecting operation andsensing operation are carried out in the DRAM array and self refreshingis effected.

Refresh timer 7402 generates refresh requesting signal /REFREQ everyprescribed period. In response, internal control signal /RAS rises to"L" to effect refreshing. Refresh address of refresh address counter7407 is incremented or decremented every refresh cycle.

When sleep mode is canceled at time t3, self refresh switching circuit7401 is reset and generation of self refresh switching signal Self isstopped. Consequently, counting operation of refresh timer 7402 is resetand prohibited.

In the structure shown in FIG. 209, self refresh switching circuit 7401monitors internal clock signal int. K and generates self refreshswitching signal Self. Self refresh switching circuit 7401 may include astructure for monitoring sleep mode control signal SLEEP. A structure inwhich refresh timer 7402 is activated in response to sleep mode controlsignal SLEEP may be used.

Further, refresh control system shown in FIG. 209 may be commonly usedwith auto refresh/self refresh switching circuit shown in FIG. 162.

FIG. 212 shows another example of circuit structure for generating sleepmode control signal SLEEP. In the structure shown in FIG. 212, sleepmode is set by external chip select signal E# and array accessdesignating signal CI# (corresponding to CC1#). Referring to FIG. 212,sleep mode control circuit 7052 includes an inverter circuit 7601receiving internal chip select signal CE#; a gate circuit 7602 receivingan output from inverter circuit 7601 and an output from gate circuit7604; an inverter circuit 7603 receiving external array accessdesignating signal CI#; a gate circuit 7604 receiving an output fromgate circuit 7602 and an output from inverter circuit 7603; and aninverter circuit 7605 receiving an output from gate circuit 7604.

FIG. 212 also shows an E buffer 7650 and CI buffer 7651 included in thecontrol clock buffer. E buffer 7650 and CI buffer 7651 take externalsignals E# and CI# at a rising edge of internal clock signal int. K,respectively and generate internal control signals E and CI.

FIG. 213 is a diagram of signal waveforms showing the operation of thecircuit shown in FIG. 212. Sleep mode setting operation will bedescribed with reference to FIGS. 199 and 200.

In the circuit structure shown in FIG. 199, sleep mode is set by acombination of external control signals E# and CI#. When chip selectsignal E# is at "H" and cache access inhibiting signal CI# is at "L",the sleep mode is set. In this state, an output from gate circuit 7602attains "H" and an output from inverter circuit 7603 attains "H". Sinceboth inputs of gate circuit 7604 are at "H" level, the circuit 7604outputs a signal at "L". Consequently, sleep mode control signal SLEEPfrom inverter circuit 7605 rises to "H".

When cache access inhibiting signal CI# rises to "H", an output fromgate circuit 7604 rises to "H" and sleep mode control signal SLEEP fallsto "L". In the structure shown in FIG. 212, length of the sleep modeperiod is determined by cache access inhibiting signal CI#.

Chip select signal E# and cache access inhibiting signal CI# are used ascontrol signals when the DRAM array is to be directly accessed (namely,when chip select signal E# is at "L" and cache access inhibiting signalCI# is at "L" at a rising edge of clock signal K in FIG. 213, the DRAMarray is directly accessed).

Therefore, in order to prevent setting of sleep mode when direct accesscycle to the array is set, a setup time Tsetup and hold time Thold isset for chip select signal E# and cache access inhibiting signal CI#, asshown in FIG. 214. Namely, referring to FIG. 214, a setup time Tsetupfrom the fall of chip select signal E# to "L" until transition of cacheaccess signal CI# to "L", and a hold time Thold from the time whenaccess inhibition signal CI# attains "H" until the time when the chipselect signal E# attains "H" are designated. When the array is accessed,cache access inhibition signal CI# changes to "L" after chip selectsignal # has changed to "L". Consequently, a state in which cache accesssignal CI# falls to "L" when chip select signal E# is "H" in directaccess to the array can be prevented, and therefore erroneous setting ofthe sleep mode can be prevented. In addition, the signal CI rises to "H"by at least the hold time T hold before the signal E# rises to "H" in anarray access setting cycle. Thus, erroneous setting of the sleep mode isalso prevented in this case.

[Summary of Internal Operation Cycle]

FIG. 215 is a table showing combinations of states of control signalsfor setting operation modes of the CDRAM. The operation modes of theCDRAM shown in FIG. 215 correspond to those shown in FIG. 51 butmodified corresponding to 3 additional functions. In the structure shownin FIG. 215, burst mode operation, high speed copy back operation anddata transfer using latches between DRAM and SRAM array are added.

The additional functions shown in FIG. 215 will be described briefly.The burst mode is set by setting control signals E#, CH# and CC2# (CR#)to "L" and control signal CC1# (CI#) to "H". The state of write enablesignal W# determines whether data writing or data reading is to becarried out. If write enable signal W# is at "H", a hit read burstoperation is carried out. If write enable signal W# is at "L", a hitwrite burst operation is carried out.

Cache hit operation as well as data transfer operation to the DRAM arrayare carried out when control signals E#, CH# and CC1# (CId) are set to"L" and control signal CC2# (CR#) is set to "H". Namely, in this state,data writing/reading is carried out between the cache (SRAM) and theCPU, and data which has been latched by latching means included in thetransfer gate are transferred to the DRAM array. The state of writeenable signal W# determines whether hit read operation or hit writeoperation is to be carried out.

In the state of a cache miss, data is transferred from the cache to thelatching means included in the transfer gate and data is transferredfrom the DRAM array to the SRAM array (cache), and data writing/readingwith the CPU is done through the cache (SRAM). This state is set bysetting chip select signal E# to "L". The write enable signal W#determines whether the operation is a miss read or miss write.

The array write operation in which data transfer from the latch(included in the data transfer gate) to the DRAM array when high speedcopy back mode operation is to be carried out, is set by setting controlsignals E# and CC2# (CR#) to "L" and control signals CH# and CC1# (CI#)to "H". In this state, data is transferred from the latch to the DRAMarray in the high speed copy back mode. By setting control signals E#,CC2# and W# to "L" and control signals CH# and CC1# (CI#) to "H", datais transferred from the cache (SRAM array) to the DRAM array.Consequently, the DRAM array is initialized.

When control signals E# and CC1# (CId) are set to "L" and controlsignals CH# and CC2# (CRY) to "H", the array can be directly accessed.Whether writing or reading of data is to be carried out is determined bywrite enable signal W#.

[Structure for Providing Optimal CDRAM]

A combination of functions effective in practice is a combination of: astructure allowing independent address designation of the DRAM and theSRAM; a structure for generating internal voltages by using continuouslyinput clock signals; a structure of a data transfer path including twoseparated paths, that is, internal data transfer path and a data writingpath; a structure for carrying out automatic refresh of the DRAM arraywhile the SRAM array is being accessed; a structure for writing data tothe DRAM array simultaneously with writing of data to the SRAM array atcache miss writing; a structure allowing selection of high speedoperation mode and low power consumption mode; a structure facilitatingconnection to the CPU having burst mode function; a structure having thesleep mode for reducing standby current; and a structure for carryingout self refreshing even in the normal mode.

The structure for generating internal voltages by the clock K is astructure in which a charge pump is operated by the clock K to generatea desired internal voltage such as substrate bias voltage.

(2) A structure of the most effective CDRAM comprises the followingfunctions: a structure allowing independent selection of a DRAM cell anda SRAM cell; a structure for generating internal voltages in accordancewith external clock signals; a structure of data transfer path havingtwo routes of internal transfer path and data writing path; high speedcopy back mode function; a structure for carrying out automaticrefreshing of the DRAM array while the SRAM array is being accessed; astructure for writing write data to the SRAM array at a cache misswriting; a structure in which SRAM addresses and DRAM column addressesare commonly used; a structure for switching methods of addressgeneration dependent on the burst mode operation; sleep mode function; astructure for carrying out self refreshing even in the normal mode; anda structure for separating data writing path from the data reading pathin the DRAM array.

[Effects of the Invention]

According to the first aspect of the present invention, switchingbetween self refresh mode and auto refresh mode is done by refresh modesetting means. In the auto refreshing mode, one terminal is used as arefresh designating input terminal, and in the self refresh mode, it isused as a self refresh execution designating output terminal. Therefore,even in the self refresh mode, refresh timing can be known outside thesemiconductor memory device, and therefore self refresh mode can beutilized even in the normal mode.

According to the second aspect of the present invention, input terminalsfor designating rows and columns of the first and second memory arraysare separately provided for inputting row addresses and columnaddresses. Consequently, the row address signals and column addresssignals can be applied in a non-multiplexed manner to the first andsecond memory arrays. A part of the address signals for the first memoryarray and a part of address signals for the second memory array areapplied to the same input terminal. Therefore, a structure in whichaddresses are applied to the first and second memory arrays in addressnon-multiplexed manner can be realized without increasing the number ofinput terminals.

According to a third aspect of the present invention, the first andsecond address signals are simultaneously taken in synchronization withexternal clock signals and internal address signals are generated.Therefore, a clock synchronized type semiconductor memory device can beoperated at high speed.

According to a fourth aspect of the present invention, data transfermeans is activated at an earlier timing than the activation timing ofsense amplifiers of the DRAM array, and data can be transferred at highspeed from the DRAM array to the SRAM array. Therefore, a CDRAM whichcan access at high speed even at a cache miss can be provided.

According to a fifth aspect of the present invention, a current mirrortype amplifier constitutes data transfer means and also potentialamplifier of the DRAM bit line, and therefore data transfer means can beactivated without waiting for activation of the latch type senseamplifier of the DRAM. Consequently, data can be transferred at highspeed from the DRAM array to the SRAM array.

According to a sixth aspect of the present invention, a counter startsits operation in response to a burst mode designation from an externaloperational processing unit, and outputs from the counter are used asaddress signals in the burst mode. Therefore, a semiconductor memorydevice which can be readily connected to an external operationalprocessing unit having burst mode function can be provided.

According to the seventh aspect of the present invention, the counterexecutes counting operation in synchronization with external clocksignals, and the counter outputs are used as addresses in the burstmode. Except the burst mode, externally applied address signals areused. Therefore, a clock synchronized type semiconductor memory devicewhich can be readily connected to an external operational processingunit having burst mode function can be realized.

According to an eighth aspect of the present invention, generation ofinternal clock signals is stopped when the clock synchronized typesemiconductor memory device is in the standby state. Consequently,operation of a circuit for taking signals in synchronization withinternal clock signals, such as a control signal input buffer, can bestopped in the standby state, and accordingly current consumption in thestandby state of the semiconductor memory device can be reduced.

According to a ninth aspect of the present invention, since self refreshmode is executed when generation of internal clock signals in theinvention in accordance with the eighth aspect, and therefore data inthe DRAM array can be surely retained even in the standby state.

According to a tenth aspect of the present invention, a row addresssignal and a column address signal are taken at the first and the secondtimings of the clock signal in a clock synchronized type semiconductormemory device, and therefore even if the clock signal has a long periodor the clock signals are generated intermittently, a semiconductormemory device which can operate at high speed can be provided.

According to an eleventh aspect of the present invention, setting meansfor previously setting timings for taking addresses of the semiconductormemory device in accordance with an address timing designating signal isprovided, and external addresses are taken in accordance with theaddress signal taking timings set in the setting means. Therefore, asemiconductor memory device which can flexibly correspond toapplications in which high speed operation is given priority andapplications in which low power consumption are given priority can beprovided.

According to the twelfth aspect, SRAM array has a multiplicate word linearchitecture, and therefore SRAM array can be easily laid out in adesired physical dimensions to provide high density and high integration

According to the thirteenth and fourteenth aspects, the clamping circuitat a data receiving side has the clamping operation in data transferbetween SRAM and DRAM, so that high speed data transfer with lesscurrent consumption can be implemented.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor memory device comprising:a DRAMarray including a plurality of dynamic type memory cells arranged in amatrix of rows and columns; an SRAM array including a plurality ofstatic type memory cells arranged in a matrix of rows and columns, eachrow of said SRAM array divided into n groups of said static type memorycells with n greater than or equal to 2, said SRAM array including aplurality of sets of n word lines each connected to memory cells of adifferent group, each set of n word lines arranged corresponding to eachrow of said SRAM array, static type memory cells on a row being arrangedin a line, and each set of n word lines arranged in parallel with acorresponding row of said static type memory cells; and data transfermeans provided between said DRAM array and SRAM array for transferringdata between a selected memory cell of said DRAM array and a selectedmemory cell of said SRAM array.
 2. A semiconductor memory deviceaccording to claim 1, whereinsaid SRAM array further includes aplurality of pairs of bit lines each pair arranged in each column ofsaid static type memory cells, a plurality of equalize/precharge meansprovided for each said pair of bit lines and responsive to aprecharge/equalize signal for precharging and equalizing a potential ofan associated pair of bit lines, and a plurality of clamping meansprovided for each said bit line and responsive to a clamping signal forclamping a potential of an associated bit line.
 3. A semiconductormemory device according to claim 2, wherein said clamping means areadapted to be inhibited from clamping when said data transfer means isactivated.
 4. A semiconductor memory device according to claim 1,wherein said data transfer means includes a plurality of transfer gatemeans each provided for n adjacent codes of said SRAM array,saidtransfer gate means simultaneously operating for data transfer betweensaid SRAM array and said DRAM array.
 5. A semiconductor memory deviceaccording to claim 4, wherein said DRAM array includes a plurality ofdata transmission lines, one for each said transfer gate means, fortransferring data between selected memory cells of DRAM array and saidtransfer gate means, and wherein each said transfer gate means includesselection means for selecting one of associated n columns of the SRAMarray in response to a group designating signal, and means fortransferring data between a column selected by said selection means andan associated data transmission line.
 6. A semiconductor memory deviceaccording to claim 2, wherein said DRAM array includes a plurality ofdata transmission lines, one for each transfer gate means, fortransferring data between the transfer gate means and selected memorycells of DRAM array, and wherein each said transfer gate means includesfirst means coupled to receive and amplify potentials on associated npairs of bit lines of SRAM array, second means for latching an output ofsaid first means, third means responsive to a first control signal fortransferring data latched in said second means to an associated datatransmission line, fourth means coupled to receive and amplify apotential on the associated data transmission line, and fifth means inresponse to a second control signal and a group designating signal forselecting one of associated n pairs of bit lines and transferring anoutput of said fourth means to thus selected pair of bit lines.
 7. Asemiconductor memory device according to claim 6, wherein said firstmeans includes logic gate means for carrying out a logical operation onpotentials received from associated bit lines.
 8. A semiconductor memorydevice according to claim 1, further comprising:read data transmissionline coupled to said transfer means driving means provided for eachcolumn of the DRAM array and responsive to a read DRAM column selectionsignal for amplifying and transferring data on a column of the DRAMarray selected by said read DRAM column selection signal to said readdata transmission line; write data transmission line provided separatelyfrom said read data transmission line and coupled to said transfer meansfor receiving data therefrom; write-in means responsive to a write DRAMcolumn selection signal for transferring data on said write datatransmission line onto a column of the DRAM array; and sense amp meansprovided separately from said driving means and for sensing, amplifyingand latching a potential on associated columns.
 9. A semiconductormemory device according to claim 8, wherein said transfer meansincludes:current supply means for supplying a current flow to said readdata transmission line; gate means responsive to a first transfer signalfor transferring data on said read data transmission line onto aselected column of the SRAM array; and write transfer means responsiveto a second transfer signal for transferring data on the selected columnof the SRAM array to said write data transmission line.
 10. Asemiconductor memory device according to claim 9, whereineach of saidcolumn of the DRAM matrix includes a pair of bit lines and said readdata transmission line includes a pair of signal lines, and said currentsupply means includes means for providing the same amount of currentflow to the pair of signal line of said read data transmission line. 11.A semiconductor memory device according to claim 10, whereinsaid drivingmeans includes a plurality of differential means provided for eachcolumn of the DRAM array and responsive to the DRAM column selectionsignal for amplifying a potential difference between an associated pairof bit lines; said differential means and said current supply meansconstituting a current mirror type amplifier in combination.
 12. Asemiconductor memory device according to claim 8, wherein said drivingmeans is adapted to be made active at an earlier timing than activationof said sense amp means.
 13. A semiconductor memory device according toclaim 8, further including:first selection means responsive to a firstaddress applied to a first address input, for generating a SRAM cellselecting signal; second selection means responsive to a second addressapplied to a second address input provided separately from said firstaddress input, for generating a DRAM row selection signal for selectinga row of the DRAM array; and third selection means responsive to a thirdaddress applied to said first address input simultaneously with saidsecond address, for generating said read DRAM column selection signaland said write DRAM column selection signal.
 14. A semiconductor memorydevice according to claim 1, further comprising:burst means responsiveto a burst mode signal for successively generating a burst address; andselection means responsive to said burst address for generating a SRAMcell selection signal for selecting a memory cell of said SRAM array.15. A semiconductor memory device according to claim 14, wherein saidburst means includesaddress generating means responsive to said burstmode signal and a received address for generating the burst addressesstarting at said received address successively, control means responsiveto said burst mode signal and the number of burst addresses generatedfrom said address generating means for defining a period of burst modeoperation; and multiplexing means responsive to said control means forselectively transferring one of a burst address and an internal addresscorresponding to an external address to said selection means.
 16. Asemiconductor memory device according to claim 15, wherein said addressgenerating means is adapted to generate a burst signal in response to aclock signal, and said control means includes defining means forcounting the clock signal to inhibit the multiplexing means fromselecting a burst address signal from said address generating means whenthe count reaches a predetermined value.
 17. A semiconductor memorydevice according to claim 16, wherein said control means includesstorage means for storing an information on the number of data accessedin the burst mode, and said defining means includes means for inhibitingsaid multiplexing means from selecting the burst address when the countcoincides with the number indicated by said information.
 18. Asemiconductor memory device according to claim 1, furtherincluding:clock generating means responsive to an external clock signalfor generating an internal clock signal; and sleep means responsive to asleep mode signal for inhibiting the clock generating means fromgenerating the internal clock, said internal clock providing timing oftaking an external signal into said memory device.
 19. A semiconductormemory device according to claim 18, whereinsaid sleep means includesmeans receiving an external signal applied asynchronously with saidexternal clock signal as said sleep mode signal and responsive theretofor generating a sleep mode indicating signal to deactivate said clockgenerating means.
 20. A semiconductor memory device according to claim18, further comprising:detecting means for detecting inhibition ofgeneration of the internal clock; request means in response to thedetection of inhibited clock generation for generating a refresh requestsignal at predetermined intervals; and refresh address means in responseto the refresh request signal for generating a refresh address forrefreshing a memory cell of the DRAM array.
 21. A semiconductor memorydevice according to claim 20, wherein said refresh address meansincludes gate means responsive to an external refresh designating signaland said refresh request signal for generating a refresh mode indicatingsignal, and refresh address generating means responsive to said refreshmode indicating signal for generating said refresh address.
 22. Asemiconductor memory device according to claim 1, furthercomprising:refresh address generating means for generating a refreshaddress for refreshing a memory cell of the DRAM array, auto-refreshmeans responsive to an external refresh mode signal for activating saidrefresh address generating means; refresh mode setting means forgenerating a mode signal setting a refresh mode of said memory device toeither an auto-refreshing mode or a self-refreshing mode; self-refreshmeans responsive to said mode signal indicating the self-refreshing modefor activating said refresh address generating means at prescribedintervals; and input/output switching means responsive to said modesignal for setting a pin terminal either to an input terminal forreceiving said external refresh mode signal or to an output terminal forsupplying a busy signal indicating that the self-refresh mode operationis carried out.
 23. A semiconductor memory device according to claim 22,whereinsaid self refresh means includes request means responsive to saidmode signal indicting the self-refresh mode for generating a refreshrequest signal at the predetermined intervals, and activating meansresponsive to said refresh request signal for activating said refreshaddress generating means, and wherein said input/output switching meansincludes means responsive to said mode signal indicating theself-refreshing for transferring said refresh request signal as saidbusy signal to said pin terminal.
 24. A semiconductor memory deviceaccording to claim 1, further comprising:row address control meansresponsive to a DRAM array access indicating signal and a clock signalfor generating a row address latch signal at a first leading edge ofsaid clock signal; column address control means responsive to the clocksignal and said row address latch signal for generating a column addresslatch signal at one of transition edges of the clock signal subsequentto said first leading edge; first latch means responsive to said rowaddress latch signal for latching an external address to generateinternal row address signal; and second latch means responsive to saidcolumn address latch signal for latching an external address to generatean internal column address.
 25. A semiconductor memory device accordingto claim 24, whereinsaid column address control means includes meansresponsive to a trailing edge of the clock signal following said firstleading edge to generate said column address latch signal.
 26. Asemiconductor memory device according to claim 24, wherein said columnaddress control means includes means for generating a setting signal forsetting a timing of latching an external address by said second latchmeans, and control means responsive to said setting signal and said rowaddress latch signal to generate said column address latch signal at oneof successive leading edges of the clock signal following the firstleading edge.
 27. A semiconductor memory device according to claim 24,further including resetting means responsive to said row address latchsignal for resetting said row address control means after elapse of apredetermined time period since generation of said row address latchsignal.
 28. A semiconductor memory device according to claim 1, furthercomprising:first address input means receiving a first address through afirst address input for generating a first internal address; secondaddress input means receiving a second address through a second addressinput for generating a second interval address; third address inputmeans receiving a third address input for generating a third internaladdress; said second address input provided separately from said thirdaddress input and receiving an address simultaneously with said thirdaddress input; first selection means responsive to said first and secondinternal address for generating a first select signal for selecting amemory of the SRAM array; second selection means responsive to saidsecond and third internal address for generating a second select signalfor selecting a memory cell of said DRAM array; and decision meansresponsive to an access indicating signal for deciding which of thefirst and second selection means receives the second internal address.29. A semiconductor memory device according to claim 28, wherein saidfirst selection means includes SRAM row selection means responsive tosaid second internal address for generating a SRAM row select signal forselecting a row of memory cells of the SRAM array, and SRAM columnselection means responsive to said first internal address for generatinga SRAM column select signal for selecting a column of memory cells ofsaid SRAM array, and said second selection means includes DRAM rowselection means responsive to said third internal address for generatinga DRAM row select signal for selecting a row of memory cells of the DRAMarray, and DRAM column select signal responsive to the second internaladdress for generating a DRAM column select signal for selecting acolumn of memory cells of the DRAM array.
 30. A semiconductor memorydevice according to claim 29, wherein said SRAM row selection meansincludes predecode means responsive to said second internal address forgenerating a predecoded signal of the second internal address, anddecoder means responsive to said predecode signal for generating saidSRAM row select signal, and whereinsaid decision means is providedbetween said predecode means and said decoder means.
 31. A semiconductormemory device according to claim 29, wherein said decision means isprovided between an output of said SRAM row selection means and an inputof said DRAM column selection means.
 32. A semiconductor memory deviceaccording to claim 30, wherein said DRAM column select means receives apart of said second internal address to generate a DRAM column selectsignal for selecting a plurality of columns of memory cells of the DRAMarray, and said SRAM column selection means selects a column amongselected plurality of codes of memory cells.
 33. A semiconductor memorydevice according to claim 1, further comprising:SRAM clamping meansprovided for each said column of said SRAM array and for clamping apotential of an associated column of said SRAM array; and control meansfor activating said data transfer means to transfer data from said DRAMarray to said SRAM array while disabling said clamping means to inhibitthe clamping operation thereof, in response to an instruction for datatransfer from said DRAM array to SRAM array.
 34. A semiconductor memorydevice according to claim 1, further including:a data transfer bus forcoupling a selected memory cell in said DRAM array to said data transfermeans; clamping means for claming a potential of said data transfer bus;and control means responsive to an instruction of data transfer fromsaid SRAM array to DRAM array, for enabling said data transfer means fordata transfer from said SRAM array to said DRAM array while disablingand clamping means to inhibit the clamping operation thereof.
 35. Asemiconductor memory device according to claim 4, wherein said DRAMarray includes a plurality of data transmission lines, one for eachtransfer gate means, for transferring data between the transfer gatemeans and selected memory cells of DRAM array, and wherein each saidtransfer gate means includes first means coupled to receive and amplifypotentials on associated n pairs of bit lines of SRAM array, secondmeans for latching an output of said first means, third means responsiveto a first control signal for transferring data latched in said secondmeans to an associated data transmission line, fourth means coupled toreceive and amplify a potential on the associated data transmissionline, and fifth means in response to a second control signal and a groupdesignating signal for selecting one of associated n pairs of bit linesand transferring an output of said fourth means to the selected pair ofbit lines.
 36. A semiconductor memory device, comprising:a first memorycell array including a plurality of memory cells arranged in a matrix ofrows and columns; a second memory cell array including a plurality ofmemory cells arranged in a matrix of rows and columns; a first rowaddress input terminal for receiving a first row address for designatinga row of said first memory cell array; a first column address inputterminal provided separate from said first row address input terminalfor receiving a first column address for designating a column of saidfirst memory cell array; a second row address input terminal forreceiving a second row address for designating a row of said secondmemory cell array; a second column address input terminal providedseparate from said second row address input terminal for receiving asecond column address for designating a column of said second memorycell array; wherein a part of said first column address input terminalis commonly used with said second row address input terminal and saidsecond column address input terminal.
 37. A semiconductor memory device,comprising:a DRAM array including a plurality of dynamic memory cellsarranged in rows and columns; an SRAM array including a plurality ofstatic memory cells arranged in a matrix of rows and columns, staticmemory cells on a row being arranged in a line, each row divided into ngroups of codes, said SRAM array including a plurality of sets of wordlines provided corresponding to the rows of said SRAM array, a differentword line in each set being connected to said static memory cells of adifferent group, each of the sets of the n word lines being arrangedcorresponding to each row of said SRAM array and in parallel with acorresponding row of said SRAM array; and data transfer means providedbetween said DRAM array and said SRAM array for transferring databetween a selected memory cell of said DRAM array and a selected memorycell of said SRAM array.
 38. A semiconductor memory device, comprising:aDRAM array including a plurality of dynamic memory cells arranged inrows and columns; an SRAM array including a plurality of static memorycells arranged in a matrix of rows and columns, each row divided into ngroups of static memory cells, said SRAM array including a plurality ofsets of immediately adjacent n word lines each connected to staticmemory cells of a different group, each set of word lines arrangedcorresponding to each row of said SRAM array and in parallel with acorresponding row of SRAM array, and static memory cells on a rowarranged in a line; and data transfer means provided between said DRAMarray and said SRAM array for transferring data between a selectedmemory cell of said DRAM array and a selected memory cell of said SRAMarray.